US4807195A
Expired / Lapsed
US
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Apparatus and method for providing a dual sense amplifier with divided bit line isolation
Assignee: International Business Machines Corp
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Filing: 1987-05-18
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Granted: 1989-02-21
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Expires: 2007-05-18
Abstract
Abstract A dual sense amplifier construction with divided bit line isolation. A switch is disposed at approximately the midpoint of a bit line to divide the bit line into first and second bit line segments. When opened, the switch provides electrical isolation between the first and second bit line segments so that an accessed memory charge can be isolated from one-half of the capacitance associated with the bit line. Once the isolated memory charge is read and pre-amplified, the remaining bit line capacitance is no longer of concern. The switch is then closed to provide electrical connection between the first and second bit line segments, thereby allowing the completion of the amplification operation.
Inventors
- 👤 Robert E. Busch
- 👤 Endre P. Thoma
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 02:33
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/18; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4091; G11C11/4097; G11C7/06; G11C7/065
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
137 words
a memory array device with divided bit line isolation, comprising: dual sense amplifier means for sensing logical memory values, said dual sense amplifier means being constructed of a first latch and a second latch; at least one bit line disposed to allow electrical interconnection between said first and second latch, said at least one bit line having a first end electrically connectable to said first latch, and a second end electrically connectable to said second latch; and switch means disposed to divide said at least one bit line into a first bit line segment and a second bit line segment, said switch means providing electrical connection between said first and second bit line segments when said switch is closed, and providing electrical isolation between said first and second bit line segments when said switch means is open.
Claim 2
Dependent Claim
137 words
a memory array device with divided bit line isolation, comprising: dual sense amplifier means for sensing logical memory values, said dual sense amplifier means being constructed of a first latch and a second latch; at least one bit line disposed to allow electrical interconnection between said first and second latch, said at least one bit line having a first end electrically connectable to said first latch, and a second end electrically connectable to said second latch; and switch means disposed to divide said at least one bit line into a first bit line segment and a second bit line segment, said switch means providing electrical connection between said first and second bit line segments when said switch is closed, and providing electrical isolation between said first and second bit line segments when said switch means is open.
Claim 3
Dependent Claim
28 words
A memory array device as claimed in claim 1, wherein said first latch is constructed of N-channel transistors, and wherein said second latch is constructed of P-channel transistors.
Claim 4
Dependent Claim
17 words
A memory array device as claimed in claim 1, wherein said switch means is of semiconductor construction.
Claim 5
Dependent Claim
24 words
A memory array device as claimed in claim 1, wherein said dual sense amplifier means and said switch means are of CMOS semiconductor construction.
Claim 6
Dependent Claim
22 words
A memory array device as claimed in claim 1, wherein there are two bit lines disposed between said first and second latch.
Claim 7
Dependent Claim
22 words
A memory array device as claimed in claim 5, wherein said two bit lines are used in a folded bit line approach.
Claim 8
Dependent Claim
45 words
A memory array device as claimed in claim 1, wherein said switch means is disposed at the center of said at least one bit line to divide said at least one bit line into a first bit line half and a second bit line half.
Claim 9
Dependent Claim
41 words
A memory array device as claimed in claim 7, wherein a plurality of bit lines is associated with said dual sense amplifier means, each of said bit lines being electrically connectable to said dual sense amplifier means by multiplexer switch means.
Claim 10
Dependent Claim
63 words
A memory array device as claimed in claim 1, wherein said at least one bit line has a plurality of memory cells disposed along its length, said switch means dividing said plurality of memory cells into a first portion of memory cells disposed along said first bit line segment, and a second portion of memory cells disposed along said second bit line segment.
Claim 11
Dependent Claim
43 words
A memory array device as claimed in claim 1, wherein said switch means is at least one field-effect transistor, the base terminal of said at least one field effect transistor being used to provide the open and closed selection of said switch means.
Claim 12
Dependent Claim
23 words
A memory array device as claimed in claim 1, wherein said switch means comprises a P-channel field-effect transistor, and an N-channel field-effect transistor.
Claim 13
Dependent Claim
190 words
A memory array device with divided bit line isolation, comprising: dual sense amplifier means for sensing logical memory values, said dual sense amplifier means being constructed of a first latch and a second latch; at least one bit line disposed to allow electrical interconnection between said first and second latch, said at least one bit line having a first end electrically connectable to said first latch, and a second end electrically connectable to said second latch, said at least one bit line having a plurality of memory cells disposed along its length; and switch means, disposed at approximately the midpoint of said at least one bit line, to divide said at least one bit line into a first bit line half having a first portion of said memory cells disposed along its length, and a second bit line half having a second portion of said memory cells disposed along its length, said switch means providing electrical connection between said first and second bit line halves when said switch is selected closed, and providing electrical isolation between said first and second bit line halves when said switch means is selected open.
Claim 14
Dependent Claim
190 words
A memory array device with divided bit line isolation, comprising: dual sense amplifier means for sensing logical memory values, said dual sense amplifier means being constructed of a first latch and a second latch; at least one bit line disposed to allow electrical interconnection between said first and second latch, said at least one bit line having a first end electrically connectable to said first latch, and a second end electrically connectable to said second latch, said at least one bit line having a plurality of memory cells disposed along its length; and switch means, disposed at approximately the midpoint of said at least one bit line, to divide said at least one bit line into a first bit line half having a first portion of said memory cells disposed along its length, and a second bit line half having a second portion of said memory cells disposed along its length, said switch means providing electrical connection between said first and second bit line halves when said switch is selected closed, and providing electrical isolation between said first and second bit line halves when said switch means is selected open.
Claim 15
Independent Claim
147 words
A method of providing a memory array device with divided bit line isolation comprising; providing dual sense amplifier means for sensing logical memory values, said sense amplifier means being constructed of a first latch and a second latch; providing at least one bit line disposed to allow electrical interconnection between said first and second latch, said at least one bit line having a first end electrically connectable to said first latch, and a second end electrically connectable to said second latch; and providing a switch means disposed to divide said at least one bit line into a first bit line segment and a second bit line segment, said switch means for providing electrical interconnection between said first and second bit line segments when said switch is selected closed, and providing electrical isolation between said first and second bit line segments when said switch means is selected open.
Claim 16
Independent Claim
147 words
A method of providing a memory array device with divided bit line isolation comprising; providing dual sense amplifier means for sensing logical memory values, said sense amplifier means being constructed of a first latch and a second latch; providing at least one bit line disposed to allow electrical interconnection between said first and second latch, said at least one bit line having a first end electrically connectable to said first latch, and a second end electrically connectable to said second latch; and providing a switch means disposed to divide said at least one bit line into a first bit line segment and a second bit line segment, said switch means for providing electrical interconnection between said first and second bit line segments when said switch is selected closed, and providing electrical isolation between said first and second bit line segments when said switch means is selected open.
Claim 17
Dependent Claim
72 words
An improved CMOS sense amplifier comprising: a P-channel latch; an N-channel latch; a pair of bit lines electrically interconnecting said latches; and a switch placed approximately at the electrical mid-point between said P-channel latch and N-channel latch in each said bit line and adapted to prevent current flow in said pair of bit lines prior to a read signal being applied to one or another half of said pair of bit lines.
Claim 18
Dependent Claim
72 words
An improved CMOS sense amplifier comprising: a P-channel latch; an N-channel latch; a pair of bit lines electrically interconnecting said latches; and a switch placed approximately at the electrical mid-point between said P-channel latch and N-channel latch in each said bit line and adapted to prevent current flow in said pair of bit lines prior to a read signal being applied to one or another half of said pair of bit lines.
Claim 19
Dependent Claim
16 words
A memory array device as claimed in claim 14, wherein said switch is of semiconductor construction.
Claim 20
Dependent Claim
23 words
A memory array device as claimed in claim 14, wherein said P-channel and N-channel latches and said switch are of CMOS semiconductor construction.
Claim 21
Dependent Claim
41 words
A memory array device as claimed in claim 14, wherein a plurality of bit lines is associated with said P-channel and N-channel latches, each of said bit lines being electrically connectable to said dual sense amplifier means by a multiplexer switch.
Claim 22
Dependent Claim
86 words
An improved sense amplifier construction comprising: a P-channel latch; an N-channel latch; a pair of bit lines electrically interconnecting said latches; and a switch placed approximately at the electrical mid-point between said P-channel latch and N-channel latch in each said bit line to divide each bit line into a first segment and a second segment, said switch being adapted to prevent current flow between said first and second segments during times when a read operation is being conducted along one of said first and second segments.
Claim 23
Dependent Claim
86 words
An improved sense amplifier construction comprising: a P-channel latch; an N-channel latch; a pair of bit lines electrically interconnecting said latches; and a switch placed approximately at the electrical mid-point between said P-channel latch and N-channel latch in each said bit line to divide each bit line into a first segment and a second segment, said switch being adapted to prevent current flow between said first and second segments during times when a read operation is being conducted along one of said first and second segments.
Claim 24
Independent Claim
107 words
A method of providing divided bit line isolation to a memory array comprising: providing a memory array having a dual sense amplifier constructed of a first latch disposed at a distance from a second latch; providing at least one bit line electrically interconnecting said first and second latches; providing switch means to divide said at least one bit line into a first bit line segment and a second bit line segment; and selecting said switch means open, during times when a read operation is being conducted along one of said first and second bit line segments, to prevent electrical current flow between said first and second segments.
Claim 25
Independent Claim
107 words
A method of providing divided bit line isolation to a memory array comprising: providing a memory array having a dual sense amplifier constructed of a first latch disposed at a distance from a second latch; providing at least one bit line electrically interconnecting said first and second latches; providing switch means to divide said at least one bit line into a first bit line segment and a second bit line segment; and selecting said switch means open, during times when a read operation is being conducted along one of said first and second bit line segments, to prevent electrical current flow between said first and second segments.
Claim 26
Dependent Claim
242 words
A memory array device with divided bit line isolation, comprising: first bit line means and second bit line means, each having first and second ends; dual sense amplifier means for sensing and amplifying, along said first and second bit line means, bit line voltages coresponding to logical memory values, said dual sense amplifier means being constructed of N-channel first latch means connectable to said first ends of said first and second bit line means and P-channel second latch means connectable to said second ends of said first and second bit line means; and switch means disposed to divide said first and second bit line means each into first and second bit line segments, said switch means providing electrical connection between respective said first and second bit line segments of each of said first and second bit line means when said switch means is closed, and providing electrical isolation between respective first and second bit line segments of each of said first and second bit line means when said switch means is open; wherein said switch means is opened to provide electrical isolation at a time prior to performing a pre-sensing and -amplifying operation with one of said first and second latch means, and then said switch means is closed to provide electrical connection to perform a complementary-sensing and -amplifying operation with an opposite one of said first and second latch means which was not used to perform said pre-sensing and -amplifying operation.
Claim 27
Dependent Claim
242 words
A memory array device with divided bit line isolation, comprising: first bit line means and second bit line means, each having first and second ends; dual sense amplifier means for sensing and amplifying, along said first and second bit line means, bit line voltages coresponding to logical memory values, said dual sense amplifier means being constructed of N-channel first latch means connectable to said first ends of said first and second bit line means and P-channel second latch means connectable to said second ends of said first and second bit line means; and switch means disposed to divide said first and second bit line means each into first and second bit line segments, said switch means providing electrical connection between respective said first and second bit line segments of each of said first and second bit line means when said switch means is closed, and providing electrical isolation between respective first and second bit line segments of each of said first and second bit line means when said switch means is open; wherein said switch means is opened to provide electrical isolation at a time prior to performing a pre-sensing and -amplifying operation with one of said first and second latch means, and then said switch means is closed to provide electrical connection to perform a complementary-sensing and -amplifying operation with an opposite one of said first and second latch means which was not used to perform said pre-sensing and -amplifying operation.
Claim 28
Independent Claim
254 words
A method of providing a memory array device with divided bit line isolation, comprising the steps of: providing first bit line means and second bit line means, each having first and second ends; providing dual sense amplifier means for sensing and amplifying, along said first and second bit line means, bitline voltages corresponding to logical memory values, said dual sense amplifier means being constructed of N-channel first latch means connectable to said first ends of said first and second bit line means and P-channel second latch means connectable to said second ends of said first and second bit line means; disposing switch means to divide said first and second bit line means each into first and second bit line segments, said switch means providing electrical connection between respective said first and second bit line segments of each of said first and second bit line means when said switch means is closed, and providing electrical isolation between respective first and second bit line segments of each of said first and second bit line means when said switch means is open; opening said switch means to provide electrical isolation at a time prior to performing a pre-sensing and -amplifying operation with one of said first and second latch means; and at a time subsequent to said pre-sensing and -amplifying, closing said switch means to provide electrical connection to perform a complementary-sensing and -amplifying operation with an opposite one of said first and second latch means which was not used to perform said pre-sensing and -amplifying operation.
Claim 29
Independent Claim
254 words
A method of providing a memory array device with divided bit line isolation, comprising the steps of: providing first bit line means and second bit line means, each having first and second ends; providing dual sense amplifier means for sensing and amplifying, along said first and second bit line means, bitline voltages corresponding to logical memory values, said dual sense amplifier means being constructed of N-channel first latch means connectable to said first ends of said first and second bit line means and P-channel second latch means connectable to said second ends of said first and second bit line means; disposing switch means to divide said first and second bit line means each into first and second bit line segments, said switch means providing electrical connection between respective said first and second bit line segments of each of said first and second bit line means when said switch means is closed, and providing electrical isolation between respective first and second bit line segments of each of said first and second bit line means when said switch means is open; opening said switch means to provide electrical isolation at a time prior to performing a pre-sensing and -amplifying operation with one of said first and second latch means; and at a time subsequent to said pre-sensing and -amplifying, closing said switch means to provide electrical connection to perform a complementary-sensing and -amplifying operation with an opposite one of said first and second latch means which was not used to perform said pre-sensing and -amplifying operation.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-02-21 | 1992-08-22 | 1993-02-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-02-21 | 1996-08-22 | 1997-02-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-02-21 | 2000-08-22 | 2001-02-21 | $7700.00 | Window Closed / Lapsed |