Patent US5483175A successfully refreshed from Google Patents.
US5483175A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for circuits connection for wafer level burning and testing of individual dies on semiconductor wafer
Assignee: Micron Technology Inc
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Filing: 1994-03-09
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Granted: 1996-01-09
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Expires: 2014-03-09
Abstract
Abstract Integrated circuit devices on a wafer are tested by the use of test circuit on the integrated circuit devices which is connected by means of a grid. The grid is used to enable the test circuitry, and provides an ability to test the devices while still on the wafer. This facilitates burning in the wafer prior to singulating the parts, since it is not necessary to separately establish electrical connections at contact points on the individual integrated circuit devices. In one embodiment, an oscillator may be adjusted in speed so that further tests may be effected by changing a test speed through the test circuit. Response of the integrated circuits at different operating speeds is determined by the adjustment of the oscillator speed so that a timing signal used for the testing may be varied.
Inventors
- 👤 Aftab Ahmad
- 👤 Larren G. Weber
- 👤 Robert S. Green
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 21:57
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/30; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/27
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
125 words
A method for testing integrated circuit devices contained on a semiconductor wafer comprising: a) forming the wafer with built in test circuitry for testing the integrated circuit devices and test enable nodes for enabling the test circuitry; b) forming a conductive grid upon the wafer including conductive traces electrically connected to power and ground connections and to the test enable nodes; c) forming the conductive traces such that at least a portion of the conductive traces can be removed to sever an electrical connection with the test enable nodes while leaving the wafer beneath said portion substantially intact; and d) removing said portion of the conductive traces by chemical mechanical planarization thereby permitting the integrated circuit devices to be operated without enabling the test circuitry.
Claim 2
Independent Claim
125 words
A method for testing integrated circuit devices contained on a semiconductor wafer comprising: a) forming the wafer with built in test circuitry for testing the integrated circuit devices and test enable nodes for enabling the test circuitry; b) forming a conductive grid upon the wafer including conductive traces electrically connected to power and ground connections and to the test enable nodes; c) forming the conductive traces such that at least a portion of the conductive traces can be removed to sever an electrical connection with the test enable nodes while leaving the wafer beneath said portion substantially intact; and d) removing said portion of the conductive traces by chemical mechanical planarization thereby permitting the integrated circuit devices to be operated without enabling the test circuitry.
Claim 3
Dependent Claim
73 words
The method as claimed in claim 1, and further comprising: a) forming a circuit as a part of the test circuit, for receiving a timing signal and for providing an error signal for indicating errors when a device under test is receiving the timing signal; and b) providing a nonvolatile memory, the nonvolatile memory being responsive to the error signal, thereby providing an indication of sequential event during which the error was detected.
Claim 4
Dependent Claim
33 words
The method as claimed in claim 1, and further comprising: providing a circuit as part of said built in test circuitry, which has at least two modes of operation including a "slow" mode.
Claim 5
Dependent Claim
53 words
The method as claimed in claim 1, and further comprising: a) forming the conductive traces on the wafer with a power supply grid and a common grid; and b) using one of said power supply and common grids to provide a test enable signal to a device under test contained on the wafer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-08 | 1999-07-10 | 2000-01-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-08 | 2003-07-10 | 2004-01-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-08 | 2007-07-10 | 2008-01-09 | $7700.00 | Window Closed / Lapsed |