Method for forming a metallurgy system having a dielectric layer that is planar and void free

Claim 1

A method of fabricating a metallurgy pattern and an overlying insulating layer having a planar surface on a semiconductor substrate comprising: providing a semiconductor substrate with a surface dielectric layer, depositing a blanket metal layer on said surface dielectric layer by chemical vapor deposition techniques at a temperature between 150° an 1000° C. and at pressure between 1×10 -3 mtorr to 1 torr, depositing a blanket insulating layer of material over the blanket metal layer, depositing, exposing and developing a photoresist layer on the blanket layer of insulating material that defines a metallurgy pattern, and exposes areas of the underlying blanket insulating layer, removing by reactive ion etching the exposed areas of the blanket insulating layer at a power of 200 to 5000 watts in a reactive plasma selected from the group consisting of CH 3 F, CF 4 and C 2 F 6 , leaving exposed areas of blanket metal layer, removing by reactive ion etching the exposed areas of blanket metal layer at a power of 200 to 5000 watts is a reactive plasma selected from the group consisting of CH 3 F, CF 4 and C 2 F 6 , depositing over the metallurgy pattern a conformal silicon oxide layer having a thickness which does not fill or close any spaces between within said metallurgy pattern using chemical vapor techniques, depositing a planarizing layer of insulating material over said conformal silicon oxide layer and etching the planarizing layer with a reactive plasma etch to at least uncover the conformal silicon oxide layer over the metallurgy pattern, and depositing a top surface conformal silicon oxide layer using chemical vapor deposition techniques, and etching via openings to the metallurgy pattern.

Claim 2

A method of fabricating a metallurgy pattern and an overlying insulating layer having a planar surface on a semiconductor substrate comprising: providing a semiconductor substrate with a surface dielectric layer, depositing a blanket metal layer on said surface dielectric layer by chemical vapor deposition techniques at a temperature between 150° an 1000° C. and at pressure between 1×10 -3 mtorr to 1 torr, depositing a blanket insulating layer of material over the blanket metal layer, depositing, exposing and developing a photoresist layer on the blanket layer of insulating material that defines a metallurgy pattern, and exposes areas of the underlying blanket insulating layer, removing by reactive ion etching the exposed areas of the blanket insulating layer at a power of 200 to 5000 watts in a reactive plasma selected from the group consisting of CH 3 F, CF 4 and C 2 F 6 , leaving exposed areas of blanket metal layer, removing by reactive ion etching the exposed areas of blanket metal layer at a power of 200 to 5000 watts is a reactive plasma selected from the group consisting of CH 3 F, CF 4 and C 2 F 6 , depositing over the metallurgy pattern a conformal silicon oxide layer having a thickness which does not fill or close any spaces between within said metallurgy pattern using chemical vapor techniques, depositing a planarizing layer of insulating material over said conformal silicon oxide layer and etching the planarizing layer with a reactive plasma etch to at least uncover the conformal silicon oxide layer over the metallurgy pattern, and depositing a top surface conformal silicon oxide layer using chemical vapor deposition techniques, and etching via openings to the metallurgy pattern.