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Patent US5482885A successfully refreshed from Google Patents.
US5482885A
Expired / Lapsed
US
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Method for forming most capacitor using poly spacer technique
Assignee: United Microelectronics Corp
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Filing: 1994-03-18
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Granted: 1996-01-09
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Expires: 2014-03-18
Abstract
Abstract A MOST capacitor for use in a DRAM cell is formed by depositing a conductive polysilicon electrode layer on the substrate. Oxide lines are then formed on the polysilicon layer. Using the oxide lines as a mask, pillars are etched in the polysilicon electrode layer.
Inventors
- 👤 Water Lur
- 👤 Cheng-Hen Huang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:40
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/30; H10B12/31; H10B12/318; H10D; H10D1/00; H10D1/01; H10D1/041; H10D1/043; H10D1/60; H10D1/68; H10D1/692; H10D1/711; H10D1/716; Y; Y10; Y10S; Y10S438/00; Y10S438/942; Y10S438/947
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
151 words
A method for forming a capacitor for use in a DRAM cell, comprising the steps of: (a) forming a conductive polysilicon electrode layer on a substrate; (b) forming an oxide layer on the polysilicon electrode layer; (c) forming oxide spaces on said oxide layer, comprising the steps of: (i) forming spaced apart nitride regions on said oxide layer; (ii) forming polysilicon spacers on the side walls of said nitride regions; (iii) removing said nitride regions; and (iv) forming said oxide spaces on the side walls of said polysilicon spacers and removing said polysilicon spacers; (d) etching said oxide spaces and said oxide layer to form oxide lines on said polysilicon electrode layer; (e) using said oxide lines as a mask, etching said polysilicon electrode layer to form pillars therein; (f) forming a dielectric layer on said polysilicon electrode layer; and (g) forming a second polysilicon electrode layer on said dielectric layer.
Claim 2
Independent Claim
151 words
A method for forming a capacitor for use in a DRAM cell, comprising the steps of: (a) forming a conductive polysilicon electrode layer on a substrate; (b) forming an oxide layer on the polysilicon electrode layer; (c) forming oxide spaces on said oxide layer, comprising the steps of: (i) forming spaced apart nitride regions on said oxide layer; (ii) forming polysilicon spacers on the side walls of said nitride regions; (iii) removing said nitride regions; and (iv) forming said oxide spaces on the side walls of said polysilicon spacers and removing said polysilicon spacers; (d) etching said oxide spaces and said oxide layer to form oxide lines on said polysilicon electrode layer; (e) using said oxide lines as a mask, etching said polysilicon electrode layer to form pillars therein; (f) forming a dielectric layer on said polysilicon electrode layer; and (g) forming a second polysilicon electrode layer on said dielectric layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-08 | 1999-07-10 | 2000-01-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-08 | 2003-07-10 | 2004-01-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-08 | 2007-07-10 | 2008-01-09 | $7700.00 | Window Closed / Lapsed |