Method of making flash EEPROM memory with reduced column leakage current

Claim 1

In a method for forming a memory device including an array of cells, where: each cell comprises first and second first conductivity type semiconductor regions, a channel semiconductor region of a second conductivity type, and a selectively chargeable gate structure including a tunnel dielectric overlying the channel region, the first conductivity type being of opposite type than the second conductivity type, the first and second regions define a controlled current path through the channel region which tends to be rendered conductive in response to a voltage level at a predetermined relationship to a gate threshold level being applied to the control gate, selectively charging the gate structure raises the gate threshold level, such that conduction of the cell in response to application to the control gate of a predetermined voltage is indicative of the logical state of the cell, and the cell is dischargeable by tunneling of electrons from the gate structure through the tunnel dielectric to the first semiconductor region to remove the charge on the gate structure, and the array is formed by the steps of: forming the cell gate structures overlying predetermined portions of an array semiconductor region of the second conductivity type corresponding to the channel regions of the cells, and forming the first and second first conductivity type regions of the cells in predetermined portions of the array semiconductor region adjacent to the channel regions, the improvement wherein, the step of forming the first and second regions of the cells comprises the steps of: after forming the gate structures, implanting a first dose of a first conductivity type dopant in the first region; and after implanting the first dose of the first conductivity type dopant in the first region, implanting a second dose of first conductivity type dopant in both the first and second regions.

Claim 22

A method of increasing the doping concentration in tunneling regions of an array of memory cells formed in a semiconductor substrate, where: each cell comprises first and second first conductivity type semiconductor regions, a channel semiconductor region of a second conductivity type, and a selectively chargeable gate structure including a tunnel dielectric overlying the channel region, the first conductivity type being of opposite type than the second conductivity type, the first and second regions define a controlled current path through the channel region which tends to be rendered conductive in response to a voltage level at a predetermined relationship to a gate threshold level being applied to the control gate, selectively charging the gate structure raises the gate threshold level, such that conduction of the cell in response to application to the control gate of a predetermined voltage is indicative of the logical state of the cell, and the cell is dischargeable by tunneling of electrons from the gate structure through the tunnel dielectric to the first semiconductor region to remove the charge on the gate structure, and the array is formed by the steps of: forming the cell gate structures overlying predetermined portions of an array semiconductor region of the second conductivity type corresponding to the channel regions of the cells, and forming the first and second first conductivity type regions of the cells in predetermined portions of the array semiconductor region adjacent to the channel regions, the improvement wherein, the step of forming the first and second regions of the cells comprises the steps of: after forming the gate structures, implanting a first dose of a first conductivity type dopant in the first region; and after implanting the first dose of the first conductivity type dopant in the first region, implanting a second dose of first conductivity type dopant in both the first and second regions.

Claim 23

A method of increasing the doping concentration in tunneling regions of an array of memory cells formed in a semiconductor substrate, where: each cell comprises first and second first conductivity type semiconductor regions, a channel semiconductor region of a second conductivity type, and a selectively chargeable gate structure including a tunnel dielectric overlying the channel region, the first conductivity type being of opposite type than the second conductivity type, the first and second regions define a controlled current path through the channel region which tends to be rendered conductive in response to a voltage level at a predetermined relationship to a gate threshold level being applied to the control gate, selectively charging the gate structure raises the gate threshold level, such that conduction of the cell in response to application to the control gate of a predetermined voltage is indicative of the logical state of the cell, and the cell is dischargeable by tunneling of electrons from the gate structure through the tunnel dielectric to the first semiconductor region to remove the charge on the gate structure, and the array is formed by the steps of: forming the cell gate structures overlying predetermined portions of an array semiconductor region of the second conductivity type corresponding to the channel regions of the cells, and forming the first and second first conductivity type regions of the cells in predetermined portions of the array semiconductor region adjacent to the channel regions, the improvement wherein, the step of forming the first and second regions of the cells comprises the steps of: after forming the gate structures, implanting a first dose of a first conductivity type dopant in the first region; and after implanting the first dose of the first conductivity type dopant in the first region, implanting a second dose of first conductivity type dopant in both the first and second regions.

Claim 24

A method of forming a memory device including an array of cells formed in a p-type array semiconductor region, where: each cell comprises first and second n-type semiconductor regions, a p-type channel semiconductor region, and a selectively chargeable gate structure overlying the channel region, the gate structure includes a tunnel dielectric disposed on the channel region, a floating gate disposed on the tunnel dielectric, a second dielectric disposed on the floating gate and a control gate disposed on the second dielectric, the first and second regions define a controlled current path through the channel region which tends to be rendered conductive in response to a voltage level at a predetermined relationship to a gate threshold level being applied to the control gate, selectively charging the gate structure raises the gate threshold level, such that conduction of the cell in response to application to the control gate of a predetermined voltage is indicative of the logical state of the cell, and the cell is dischargeable by Fowler-Nordheim tunneling of electrons from the gate structure through the tunnel dielectric to the first semiconductor region the method including the steps of: forming a field oxide on first predetermined areas of the array semiconductor region; forming the gate dielectric on second predetermined areas of the array semiconductor region; the first and second predetermined areas being relatively disposed in alternating strips in a first direction such that the entire array semiconductor region within the array is covered with one of the gate dielectric and the field oxide; forming a plurality of the gate structures on the tunnel dielectric by performing the steps of: depositing a first layer of polysilicon on the tunnel dielectric and on the field oxide; applying a first mask to the first layer of polysilicon to protect the first layer of polysilicon substantially overlying the gate dielectric; etching the first layer of polysilicon to remove the first layer of polysilicon substantially overlying the field oxide; removing the first mask; depositing a second dielectric over the first layer of polysilicon and over the field oxide; depositing a second layer of polysilicon on the second dielectric; applying a second mask to the second layer of polysilicon to protect strips of the second layer of polysilicon in a second direction perpendicular to the first direction; etching the second layer of polysilicon, the second dielectric, and the first layer of polysilicon, to form word lines of the second layer of polysilicon in strips in the second direction and to form individual floating gates formed of the first layer of polysilicon at predetermined relative dispositions corresponding to the channel regions of the cells; removing the second mask; applying a third mask with edges aligned on the word lines to cover the second regions and to expose the field oxide between the first regions; selectively etching the word lines and exposed field oxide to remove the field oxide at a much faster rate than the polysilicon in the word lines is removed; implanting a first dose of an n+ dopant in the first region; removing the third mask; heating the device at a predetermined elevated temperature for a predetermined period of time to drive the first dose of the n+ dopant into the array semiconductor region underlying the floating gate; implanting a second dose of the n+ dopant in the first and second regions, to develop a resultant n+ doping concentration in the first region that is higher than the resultant n+ doping concentration in the second region.

Claim 25

A method of forming a memory device including an array of cells formed in a p-type array semiconductor region, where: each cell comprises first and second n-type semiconductor regions, a p-type channel semiconductor region, and a selectively chargeable gate structure overlying the channel region, the gate structure includes a tunnel dielectric disposed on the channel region, a floating gate disposed on the tunnel dielectric, a second dielectric disposed on the floating gate and a control gate disposed on the second dielectric, the first and second regions define a controlled current path through the channel region which tends to be rendered conductive in response to a voltage level at a predetermined relationship to a gate threshold level being applied to the control gate, selectively charging the gate structure raises the gate threshold level, such that conduction of the cell in response to application to the control gate of a predetermined voltage is indicative of the logical state of the cell, and the cell is dischargeable by Fowler-Nordheim tunneling of electrons from the gate structure through the tunnel dielectric to the first semiconductor region the method including the steps of: forming a field oxide on first predetermined areas of the array semiconductor region; forming the gate dielectric on second predetermined areas of the array semiconductor region; the first and second predetermined areas being relatively disposed in alternating strips in a first direction such that the entire array semiconductor region within the array is covered with one of the gate dielectric and the field oxide; forming a plurality of the gate structures on the tunnel dielectric by performing the steps of: depositing a first layer of polysilicon on the tunnel dielectric and on the field oxide; applying a first mask to the first layer of polysilicon to protect the first layer of polysilicon substantially overlying the gate dielectric; etching the first layer of polysilicon to remove the first layer of polysilicon substantially overlying the field oxide; removing the first mask; depositing a second dielectric over the first layer of polysilicon and over the field oxide; depositing a second layer of polysilicon on the second dielectric; applying a second mask to the second layer of polysilicon to protect strips of the second layer of polysilicon in a second direction perpendicular to the first direction; etching the second layer of polysilicon, the second dielectric, and the first layer of polysilicon, to form word lines of the second layer of polysilicon in strips in the second direction and to form individual floating gates formed of the first layer of polysilicon at predetermined relative dispositions corresponding to the channel regions of the cells; removing the second mask; applying a third mask with edges aligned on the word lines to cover the second regions and to expose the field oxide between the first regions; selectively etching the word lines and exposed field oxide to remove the field oxide at a much faster rate than the polysilicon in the word lines is removed; implanting a first dose of an n+ dopant in the first region; removing the third mask; heating the device at a predetermined elevated temperature for a predetermined period of time to drive the first dose of the n+ dopant into the array semiconductor region underlying the floating gate; implanting a second dose of the n+ dopant in the first and second regions, to develop a resultant n+ doping concentration in the first region that is higher than the resultant n+ doping concentration in the second region.

Claim 26

A method of forming a memory device including an array of cells formed at least in part in a p-type semiconductor array semiconductor region, where: each cell comprises first and second n-type semiconductor regions, a p-type channel semiconductor region, and a selectively chargeable gate structure overlying the channel region, the gate structure includes a tunnel dielectric disposed on the channel region, a floating gate disposed on the tunnel dielectric, a second dielectric disposed on the floating gate and a control gate disposed on the second dielectric, the first and second regions define a controlled current path through the channel region which tends to be rendered conductive in response to a voltage level at a predetermined relationship to a gate threshold level being applied to the control gate, selectively charging the gate structure raises the gate threshold level, such that conduction of the cell in response to application to the control gate of a predetermined voltage is indicative of the logical state of the cell, and the cell is dischargeable by Fowler-Nordheim tunneling of electrons from the gate structure through the tunnel dielectric to the first semiconductor region the method including the steps of: forming a field oxide on first predetermined areas of the array semiconductor region; forming the gate dielectric on second predetermined areas of the array semiconductor region; the first and second predetermined areas being relatively disposed in alternating strips in a first direction such that the entire array semiconductor region within the array is covered with one of the gate dielectric and the field oxide; forming a plurality of the gate structures on the tunnel dielectric by performing the steps of: depositing a first layer of polysilicon on the tunnel dielectric and on the field oxide; applying a first mask to the first layer of polysilicon to protect the first layer of polysilicon substantially overlying the gate dielectric; etching the first layer of polysilicon to remove the first layer of polysilicon substantially overlying the field oxide; removing the first mask; depositing a second dielectric over the first layer of polysilicon and over the field oxide; depositing a second layer of polysilicon on the second dielectric; applying a second mask to the second layer of polysilicon to protect strips of the second layer of polysilicon in a second direction perpendicular to the first direction; etching the second layer of polysilicon, the second dielectric, and the first layer of polysilicon, to form word lines of the second layer of polysilicon in strips in the second direction and to form individual floating gates formed of the first layer of polysilicon at predetermined relative dispositions corresponding to the channel regions of the cells; removing the second mask; applying a third mask with edges aligned on the word lines to cover the second regions and to expose the field oxide between the first regions; selectively etching the word lines and exposed field oxide to remove the field oxide at a much faster rate than the polysilicon in the word lines is removed; implanting a first dose of an n+ dopant in the first region; removing the third mask; implanting a first dose of an n+ dopant in the first and second regions at a positive angle of 20 to 40 degrees with respect to an axis normal to the array semiconductor region; and implanting a second dose of the n+ dopant in the first and second regions at a negative angle of 20 to 40 degrees with respect to the normal axis.

Claim 27

A method of forming a memory device including an array of cells formed at least in part in a p-type semiconductor array semiconductor region, where: each cell comprises first and second n-type semiconductor regions, a p-type channel semiconductor region, and a selectively chargeable gate structure overlying the channel region, the gate structure includes a tunnel dielectric disposed on the channel region, a floating gate disposed on the tunnel dielectric, a second dielectric disposed on the floating gate and a control gate disposed on the second dielectric, the first and second regions define a controlled current path through the channel region which tends to be rendered conductive in response to a voltage level at a predetermined relationship to a gate threshold level being applied to the control gate, selectively charging the gate structure raises the gate threshold level, such that conduction of the cell in response to application to the control gate of a predetermined voltage is indicative of the logical state of the cell, and the cell is dischargeable by Fowler-Nordheim tunneling of electrons from the gate structure through the tunnel dielectric to the first semiconductor region the method including the steps of: forming a field oxide on first predetermined areas of the array semiconductor region; forming the gate dielectric on second predetermined areas of the array semiconductor region; the first and second predetermined areas being relatively disposed in alternating strips in a first direction such that the entire array semiconductor region within the array is covered with one of the gate dielectric and the field oxide; forming a plurality of the gate structures on the tunnel dielectric by performing the steps of: depositing a first layer of polysilicon on the tunnel dielectric and on the field oxide; applying a first mask to the first layer of polysilicon to protect the first layer of polysilicon substantially overlying the gate dielectric; etching the first layer of polysilicon to remove the first layer of polysilicon substantially overlying the field oxide; removing the first mask; depositing a second dielectric over the first layer of polysilicon and over the field oxide; depositing a second layer of polysilicon on the second dielectric; applying a second mask to the second layer of polysilicon to protect strips of the second layer of polysilicon in a second direction perpendicular to the first direction; etching the second layer of polysilicon, the second dielectric, and the first layer of polysilicon, to form word lines of the second layer of polysilicon in strips in the second direction and to form individual floating gates formed of the first layer of polysilicon at predetermined relative dispositions corresponding to the channel regions of the cells; removing the second mask; applying a third mask with edges aligned on the word lines to cover the second regions and to expose the field oxide between the first regions; selectively etching the word lines and exposed field oxide to remove the field oxide at a much faster rate than the polysilicon in the word lines is removed; implanting a first dose of an n+ dopant in the first region; removing the third mask; implanting a first dose of an n+ dopant in the first and second regions at a positive angle of 20 to 40 degrees with respect to an axis normal to the array semiconductor region; and implanting a second dose of the n+ dopant in the first and second regions at a negative angle of 20 to 40 degrees with respect to the normal axis.