Programmable binary/interleave sequence counter

Claim 2

A counter circuit for sequential address generation comprising: a mode select input; a toggle control circuit responsively coupled to said mode select input; an interleave state control circuit coupled to said toggle control circuit; a first counter responsively coupled to said toggle control circuit and providing a sequence of count values in a progression corresponding to a select signal applied to said mode select input; wherein said toggle control circuit includes logic circuits and provides control signals to said counter based on the select signal; wherein said interleave control circuit includes a second counter; wherein said toggle control circuit is coupled to receive a lower order count signal for use in generating a binary sequence; wherein said interleave state control circuit provides interleave control signals; and wherein said toggle control circuit selectively provides a signal corresponding to the lower order count signal or to the interleave control signal for use by the first counter.

Claim 3

The counter circuit of claim 1 wherein said first counter comprises a plurality of toggle flip-flops each providing a respective count bit to a count output, each toggle flip-flop having a respective toggle input; and wherein said toggle control circuit provides control signals for at least one of said toggle flip-flops.

Claim 4

The counter circuit of claim 2 wherein said toggle flip-flops include data inputs for receiving starting count data, load enable inputs for controlling the loading of said data, and clock inputs for receiving a clock signal.

Claim 5

The counter circuit of claim 3 wherein said second counter comprises first and second toggle flip-flops, said second toggle flip-flop being responsively coupled to said first toggle flip-flop; wherein said first and second toggle flip-flops are coupled to said toggle control circuit to provide toggle signals thereto; said interleave control circuit further including an interleave reset input coupled to said first and second toggle flip-flops.

Claim 6

A programmable counter circuit for sequential address generation comprising: a plurality of controllable counting stages providing output bits to a count output, the counting stages having orders of significance from a lowest order to a highest order; an interleave control circuit configured to provide interleave signals for counting in an interleave sequence; a select input to receive a select signal; a first control circuit coupled to said select input and responsive to said select signal to select between control signals for binary counting or interleave counting, the first control circuit being controllingly coupled to an input of at least one of the higher order counting stages, the first control circuit being coupled to receive an output of at least one of the lower order counting stages and coupled to receive said interleave signals; and wherein said first control circuit controls at least one of said counting stages to count values in a binary progression or an interleave progression depending on the state of the select signal.

Claim 7

A programmable counter circuit for sequential address generation comprising: a plurality of controllable counting stages providing output bits to a count output, the counting stages having orders of significance from a lowest order to a highest order; an interleave control circuit configured to provide interleave signals for counting in an interleave sequence; a select input to receive a select signal; a first control circuit coupled to said select input and responsive to said select signal to select between control signals for binary counting or interleave counting, the first control circuit being controllingly coupled to an input of at least one of the higher order counting stages, the first control circuit being coupled to receive an output of at least one of the lower order counting stages and coupled to receive said interleave signals; and wherein said first control circuit controls at least one of said counting stages to count values in a binary progression or an interleave progression depending on the state of the select signal.

Claim 8

The counter circuit according to claim 5 wherein said counter circuit further comprises a data input for setting a count value.

Claim 9

The counter circuit according to claim 5 wherein said counting stages include a plurality of latches.

Claim 10

The counter circuit according to claim 7 wherein each said counting stage comprises a toggle flip-flop; and wherein both said first control circuit and interleave control circuit are configured to provide toggle control signals which are coupled to said toggle flip-flops.

Claim 11

The counter circuit according to claim 5 wherein said interleave control circuit includes an interleave reset input.

Claim 12

The counter circuit according to claim 5 wherein said first control circuit includes a mode-select circuit comprising a multiplexer circuit.

Claim 13

The counter circuit according to claim 5 wherein two of said count output bits are coupled to said first control circuit for providing binary count control signals.

Claim 14

A counter circuit according to claim 7 wherein said counter circuit is used in semiconductor memory devices to generate a stream of addresses in one of a binary count progression and an interleave count progression; wherein multiple data accesses may be made with a single address load for multiple memory accesses.

Claim 17

The method according to claim 13 wherein the step of controlling the count stages in the interleave sequence includes generating a further count sequence for use as control signals for the count stages.

Claim 18

The method of claim 14 wherein said further count sequence is a binary sequence.

Claim 19

The method according to claim 13 wherein the method for generating includes receiving the initial count value from a data input and loading the initial count value into said count stages.

Claim 22

The method of claim 17 wherein said method includes using further count stages for internally generating the interleave toggle control signals.

Claim 23

The method of claim 18 wherein said step of using further count stages includes resetting the further count stages in response to an interleave reset signal.

Claim 24

The method of claim 18 wherein said steps of selectively using include selectively passing either said binary toggle control signals or said interleave toggle control signals to toggle the count stages.

Claim 25

The method of claim 18 wherein said internally generating step comprises internally generating a binary sequence.