System with reduced instruction set processor accessing plural memories at different speeds using bank interleaving

Claim 2

A data processor, comprising: a central processing unit including an instruction bus and a data bus controllable independently of each other and capable of processing one instruction in one clock cycle; an instruction memory connected to said instruction bus for storing an instruction to be executed by said central processing unit; a data memory connected to said data bus for storing data to be processed by said central processing unit in accordance with said instruction; first control means for controlling said central processing unit to make access to said instruction memory with no wait states; and second control means for controlling said central processing unit to make access to said data memory with one wait state.

Claim 3

The data processor according to claim 1, wherein said instruction memory includes a plurality of banks, and said first control means controls said instruction memory so that said plurality of banks are accessed by turns by said central processing unit.

Claim 4

The data processor according to claim 1, wherein said central processing unit applies address information of said instruction memory to said first control means, and said first control means controls said instruction memory to increment said address information in a predetermined cycle and access an address corresponding to the incremented result.

Claim 5

The data processor according to claim 1, wherein said instruction memory comprises an EPROM.

Claim 6

The data processor according to claim 1, wherein said data memory comprises a DRAM.

Claim 7

The data processor according to claim 1, further comprising, an address bus for connecting said central processing unit and said first and second control means.

Claim 8

A data processor, comprising: clock signal generating means for generating a clock signal of a predetermined cycle; a RISC (Reduced Instruction Set Computer) type CPU for executing a predetermined program in synchronization with said clock signal and capable of processing one instruction in one clock cycle defined by said clock signal; an instruction memory for storing therein an instruction to be executed by said CPU; a data memory for storing therein data to be processed by said CPU in accordance with said instruction; first control means for controlling said CPU and said instruction memory so as to cause said CPU to make access to said instruction memory for each one clock cycle; and second control means for controlling said CPU and said data memory so as to cause said CPU to make access to said data memory for every two clock cycles.

Claim 9

A data processor, comprising: clock signal generating means for generating a clock signal of a predetermined cycle; a RISC (Reduced Instruction Set Computer) type CPU for executing a predetermined program in synchronization with said clock signal and capable of processing one instruction in one clock cycle defined by said clock signal; an instruction memory for storing therein an instruction to be executed by said CPU; a data memory for storing therein data to be processed by said CPU in accordance with said instruction; first control means for controlling said CPU and said instruction memory so as to cause said CPU to make access to said instruction memory for each one clock cycle; and second control means for controlling said CPU and said data memory so as to cause said CPU to make access to said data memory for every two clock cycles.

Claim 10

The data processor according to claim 7, further comprising, an instruction bus for connecting said CPU and said instruction memory, and a data bus for connecting said CPU and said data memory.

Claim 11

The data processor according to claim 8, further comprising, an address bus for connecting said CPU and said first and second control means, wherein said CPU makes access to said instruction memory in a burst mode.

Claim 12

The data processor according to claim 9, wherein said instruction memory includes a plurality of banks, and said first control means controls said instruction memory by a bank interleave method.

Claim 13

A data processor, comprising: clock signal generating means for generating a clock signal with a predetermined frequency; central processing means including an instruction bus and a data bus for executing a predetermined program in synchronization with said clock signal and capable of processing one instruction in one cycle of said clock signal; an instruction memory connected to said instruction bus for storing an instruction to be executed by said central processing means; a data memory connected to said data bus for storing data to be processed by said central processing means in accordance with said instruction, said central processing means including means for generating an instruction access request signal and means for generating a data access request signal; first control means for controlling said central processing means and said instruction memory so as to cause said central processing means to read the instruction stored in said instruction memory before time corresponding to said one cycle has elapsed after generation of said instruction access request signal; and second control means for controlling said central processing means and said data memory so as to cause said central processing means to write or read data into or from said data memory during a time period between the time that the time corresponding to said one cycle has elapsed and the time that time corresponding to a subsequent one cycle has elapsed, after generation of said data access request signal.

Claim 14

A data processor, comprising: clock signal generating means for generating a clock signal with a predetermined frequency; central processing means including an instruction bus and a data bus for executing a predetermined program in synchronization with said clock signal and capable of processing one instruction in one cycle of said clock signal; an instruction memory connected to said instruction bus for storing an instruction to be executed by said central processing means; a data memory connected to said data bus for storing data to be processed by said central processing means in accordance with said instruction, said central processing means including means for generating an instruction access request signal and means for generating a data access request signal; first control means for controlling said central processing means and said instruction memory so as to cause said central processing means to read the instruction stored in said instruction memory before time corresponding to said one cycle has elapsed after generation of said instruction access request signal; and second control means for controlling said central processing means and said data memory so as to cause said central processing means to write or read data into or from said data memory during a time period between the time that the time corresponding to said one cycle has elapsed and the time that time corresponding to a subsequent one cycle has elapsed, after generation of said data access request signal.

Claim 15

The data processor according to claim 11, wherein said central processing means includes an RISC type microprocessor, and said predetermined frequency is lower than a rated operating frequency of said microprocessor.

Claim 16

A data processor, comprising: clock signal generating means for generating a clock signal of a predetermined cycle; a RISC (Reduced Instruction Set Computer) type CPU including an instruction bus and a data bus controllable independently of each other for executing a predetermined program in synchronization with said clock signal and capable of processing one instruction in one clock cycle defined by said clock signal; an instruction memory connected to said instruction bus and including a plurality of banks, each of said banks storing an instruction to be executed by said CPU; a data memory connected to said data bus for storing data to be processed by said CPU in accordance with said instruction, said CPU including means for generating an instruction access request signal and means for generating a data access request signal, and making access to said instruction memory in a burst mode; first control means for controlling said CPU and said instruction memory so as to cause said CPU to read the instruction stored in said instruction memory before time corresponding to said one cycle has elapsed after generation of said instruction access request signal, said first control means controlling said instruction memory by a bank interleave method; and second control means for controlling said CPU and said data memory so as to cause said CPU to write or read data into or from said data memory during a time period between the time that the time corresponding to said one cycle has elapsed and the time that time corresponding to a subsequent one cycle has elapsed, after generation of said data access request signal.

Claim 17

A data processor, comprising: clock signal generating means for generating a clock signal of a predetermined cycle; a RISC (Reduced Instruction Set Computer) type CPU including an instruction bus and a data bus controllable independently of each other for executing a predetermined program in synchronization with said clock signal and capable of processing one instruction in one clock cycle defined by said clock signal; an instruction memory connected to said instruction bus and including a plurality of banks, each of said banks storing an instruction to be executed by said CPU; a data memory connected to said data bus for storing data to be processed by said CPU in accordance with said instruction, said CPU including means for generating an instruction access request signal and means for generating a data access request signal, and making access to said instruction memory in a burst mode; first control means for controlling said CPU and said instruction memory so as to cause said CPU to read the instruction stored in said instruction memory before time corresponding to said one cycle has elapsed after generation of said instruction access request signal, said first control means controlling said instruction memory by a bank interleave method; and second control means for controlling said CPU and said data memory so as to cause said CPU to write or read data into or from said data memory during a time period between the time that the time corresponding to said one cycle has elapsed and the time that time corresponding to a subsequent one cycle has elapsed, after generation of said data access request signal.

Claim 18

The data processor according to claim 13, wherein said first control means applies a first access permitting signal to said CPU before the time corresponding to said one cycle has elapsed after the generation of said instruction access request signal, said second control means applies a second access permitting signal to said CPU during the time period between the time that the time corresponding to said one cycle has elapsed and the time that the time corresponding to the subsequent one cycle has elapsed, after the generation of said data access request signal, and said CPU reads the instruction from said instruction memory in response to said first access permitting signal and writes or reads data into or from said data memory in response to said second access permitting signal.

Claim 19

A control method of a data processor, said data processor including, a central processing unit having an instruction bus and a data bus controllable independently of each other and capable of processing one instruction in one clock cycle, an instruction memory connected to said instruction bus for storing an instruction to be executed by said central processing unit, and a data memory connected to said data bus for storing data to be processed by said central processing unit in accordance with said instruction, said method comprising: a first step of controlling said central processing unit to make access to said instruction memory with no wait states; and a second step of controlling said central processing unit to make access to said data memory with one wait state.

Claim 20

A control method of a data processor, said data processor including, a central processing unit having an instruction bus and a data bus controllable independently of each other and capable of processing one instruction in one clock cycle, an instruction memory connected to said instruction bus for storing an instruction to be executed by said central processing unit, and a data memory connected to said data bus for storing data to be processed by said central processing unit in accordance with said instruction, said method comprising: a first step of controlling said central processing unit to make access to said instruction memory with no wait states; and a second step of controlling said central processing unit to make access to said data memory with one wait state.

Claim 21

The control method according to claim 15, wherein said central processing unit makes access to said instruction memory in a burst mode in said first step.

Claim 22

The control method according to claim 16, wherein said instruction memory is controlled by a bank interleave method in said first step.

Claim 23

A data processor, comprising: clock signal generating means for generating a clock signal of a predetermined cycle; a microprocessor for executing a predetermined program in synchronization with said clock signal; a memory for storing data therein; and control means connected to said microprocessor and said memory for controlling timing to write or read data into or from said memory in response to an access request signal generated from said microprocessor, said predetermined cycle being lower than a rated operating frequency of said microprocessor, said control means controlling said timing so that the number of wait states in making access to said memory is lower than the number of wait states required for making access to said memory when said microprocessor is operated at the rated operating frequency.

Claim 24

A data processor, comprising: clock signal generating means for generating a clock signal of a predetermined cycle; a microprocessor for executing a predetermined program in synchronization with said clock signal; a memory for storing data therein; and control means connected to said microprocessor and said memory for controlling timing to write or read data into or from said memory in response to an access request signal generated from said microprocessor, said predetermined cycle being lower than a rated operating frequency of said microprocessor, said control means controlling said timing so that the number of wait states in making access to said memory is lower than the number of wait states required for making access to said memory when said microprocessor is operated at the rated operating frequency.

Claim 25

The data processor according to claim 18, wherein said microprocessor comprises an RISC (Reduced Instruction Set Computer) type CPU capable of processing one instruction in one clock cycle defined by said clock signal.

Claim 26

The data processor according to claim 19, wherein said memory comprises a DRAM.

Claim 27

The data processor according to claim 18, wherein said memory includes, an instruction memory connected via an instruction bus to said microprocessor, for storing an instruction instructing the processing content to be executed by said microprocessor, and a data memory connected via a data bus to said microprocessor, for storing data to be processed by said microprocessor in accordance with said instruction.

Claim 28

The data processor according to claim 21, wherein said control means controls said microprocessor, said instruction memory and said data memory so that the number of wait states in making access to said data memory is higher than the number of wait states in making access to said instruction memory.

Claim 29

The data processor according to claim 21, wherein said microprocessor comprises an RISC (Reduced Instruction Set Computer) type CPU capable of processing one instruction in one clock cycle defined by said clock signal, and said control means controls said microprocessor so as to make access to said instruction memory with no wait states and to said data memory with one wait state.

Claim 30

A data processor, comprising: clock signal generating means for generating a clock signal of a predetermined cycle; a microprocessor capable of processing one instruction in one clock cycle defined by said clock signal and executing a predetermined program in synchronization with said clock signal; a memory for storing data therein, wherein time required to make access to said memory is longer than one cycle of a rated operating frequency of said microprocessor; and control means connected to said microprocessor and said memory for controlling timing to write or read data into or from said memory in response to an access request signal generated from said microprocessor, said predetermined cycle being lower than the rated operating frequency of said microprocessor, said control means controlling said timing so that the number of wait states in making access to said memory is lower than the number of wait states required for making access to said memory when said microprocessor is operated at the rated operating frequency.

Claim 31

A data processor, comprising: clock signal generating means for generating a clock signal of a predetermined cycle; a microprocessor capable of processing one instruction in one clock cycle defined by said clock signal and executing a predetermined program in synchronization with said clock signal; a memory for storing data therein, wherein time required to make access to said memory is longer than one cycle of a rated operating frequency of said microprocessor; and control means connected to said microprocessor and said memory for controlling timing to write or read data into or from said memory in response to an access request signal generated from said microprocessor, said predetermined cycle being lower than the rated operating frequency of said microprocessor, said control means controlling said timing so that the number of wait states in making access to said memory is lower than the number of wait states required for making access to said memory when said microprocessor is operated at the rated operating frequency.

Claim 32

The data processor according to claim 24, wherein said memory includes, an instruction memory connected via an instruction bus to said microprocessor, for storing an instruction instructing the processing content to be executed by said microprocessor, and a data memory connected via a data bus to said microprocessor, for storing data to be processed by said microprocessor in accordance with said instruction.

Claim 33

The data processor according to claim 25, wherein said control means controls said microprocessor, said instruction memory and said data memory so as to cause said microprocessor to access said instruction memory with no wait states and said data memory with one wait state.

Claim 34

The data processor according to claim 26, wherein said instruction memory includes a plurality of banks, and said control means controls said instruction memory to cause said microprocessor to access said plurality of banks by turns.

Claim 35

The data processor according to claim 27, wherein said microprocessor applies address information of said instruction memory to said control means, and said control means controls said instruction memory to increment said address information in a predetermined cycle and to access an address corresponding to the incremented result.