US5287470A
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US
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Apparatus and method for coupling a multi-lead output bus to interleaved memories, which are addressable in normal and block-write modes
Assignee: Texas Instruments Inc
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Filing: 1989-12-28
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Granted: 1994-02-15
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Expires: 2009-12-28
Abstract
Abstract A circuit and method of operation for controlling block-write operations to interleaved memories is disclosed which includes first and second interleave banks of memories, each memory addressable in a normal mode in a block-write mode. Each memory has a plurality of input nodes for receiving data in a normal mode, ones of the input nodes operable to receive data in the block-write mode and other ones of said input nodes not used in the block-write mode. Coupling circuitry couples leads from an output bus to input nodes of the first bank memories which are operable to receive data in the block-write mode and to input nodes in the second bank of memories which are not used in the block-write mode.
Inventors
- 👤 Richard D. Simpson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 07:56
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0607; G09; G09G; G09G5/00; G09G5/36; G09G5/39; G09G5/393
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
149 words
A processing system, supporting block-write functions, comprising: first and second interleaved banks of memories, said first and second interleaved banks of memories each including an identical predetermined number of memories, each memory having a block-write data register, each memory addressable in a normal mode and a block-write mode and each memory having a plurality of input nodes for receiving data in said normal mode, a first subset of said input nodes operable to receive control data in said block-write mode controlling writing of data into said memory from said block-write data register and a second subset of said input nodes not used in said block-write mode; a multi-lead output bus; and coupling circuitry operable to couple ones of said output bus leads to input nodes of said first subset of said first bank of memories and to inputs nodes of said second subset of said second bank of memories.
Claim 2
Dependent Claim
149 words
A processing system, supporting block-write functions, comprising: first and second interleaved banks of memories, said first and second interleaved banks of memories each including an identical predetermined number of memories, each memory having a block-write data register, each memory addressable in a normal mode and a block-write mode and each memory having a plurality of input nodes for receiving data in said normal mode, a first subset of said input nodes operable to receive control data in said block-write mode controlling writing of data into said memory from said block-write data register and a second subset of said input nodes not used in said block-write mode; a multi-lead output bus; and coupling circuitry operable to couple ones of said output bus leads to input nodes of said first subset of said first bank of memories and to inputs nodes of said second subset of said second bank of memories.
Claim 3
Dependent Claim
49 words
The processing system of claim 1 wherein said coupling circuit is further operable to couple other ones of said output bus leads to input nodes of said first subset of said second bank of memories and to input nodes of said second subset in said first bank of memories.
Claim 4
Dependent Claim
82 words
The processing system of claim 1 and further comprising: a multi-lead input bus for receiving data from an external source; and reordering circuitry for passing data from said leads of said input bus to certain leads of said output bus when data is presented to said memories in normal mode and for passing control data from said leads of said input bus to certain other leads of said output bus when control data is presented to said memories in a block-write mode.
Claim 5
Dependent Claim
14 words
The processing system of claim 3 wherein said reordering circuitry is a multiplex circuit.
Claim 6
Dependent Claim
26 words
The processing system of claim 3 wherein said reordering circuitry includes a memory having a look-up table for the association of input leads to output leads.
Claim 7
Dependent Claim
23 words
The processing system of claim 3 wherein said reordering circuitry includes circuitry for passing data from individual input leads to multiple output leads.
Claim 8
Dependent Claim
30 words
The processing system of claim 3 wherein said memories contain video display pixel data, and wherein said reordering circuitry controls a single pixel value split between more than one memory.
Claim 9
Dependent Claim
55 words
The processing system of claim 1 wherein said first and second interleaved banks of memories each comprise n corresponding memories, each memory having m input nodes including p input nodes of said first subset and at least p input nodes of said second subset, and wherein m is equal to or greater than 2 p.
Claim 10
Dependent Claim
54 words
The processing system of claim 8 wherein said coupling circuitry is operable to couple a first subset of said leads of said output bus to respective input nodes of said first subset of each memory bank and a second subset of leads of said output bus to respective input nodes of said second subset.
Claim 11
Independent Claim
153 words
A method of controlling block-write access in a processing system comprising the steps of: storing data in first and second interleaved banks of memories, said first and second interleaved banks of memories each including an identical predetermined number of memories, each memory having a block-write data register, each memory addressable in a normal mode and a block-write mode and each memory having a plurality of input nodes for receiving data in said normal mode, a first subset of said input nodes operable to receive control data in said block-write mode controlling writing of data into said memory from said block-write data register and a second subset of said input nodes not used in said block-write mode; and coupling a plurality of leads of an output bus to input nodes of said first subset of said first bank of memories and to inputs nodes of said second subset of said second bank of memories.
Claim 12
Independent Claim
153 words
A method of controlling block-write access in a processing system comprising the steps of: storing data in first and second interleaved banks of memories, said first and second interleaved banks of memories each including an identical predetermined number of memories, each memory having a block-write data register, each memory addressable in a normal mode and a block-write mode and each memory having a plurality of input nodes for receiving data in said normal mode, a first subset of said input nodes operable to receive control data in said block-write mode controlling writing of data into said memory from said block-write data register and a second subset of said input nodes not used in said block-write mode; and coupling a plurality of leads of an output bus to input nodes of said first subset of said first bank of memories and to inputs nodes of said second subset of said second bank of memories.
Claim 13
Dependent Claim
45 words
The processing system of claim 10 wherein said coupling step further couples other leads of said output bus to input nodes of said first subset of said second bank of memories and to input nodes of said second subset in said first bank of memories.
Claim 14
Dependent Claim
73 words
The method of claim 1 and further comprising the steps of: passing data from the leads of an input bus to certain leads of said output bus when data is being presented to the memories in a normal mode; and reordering control data to pass from the leads of said input bus to certain other leads of said output bus when control data is being presented to said memories in a block-write mode.
Claim 15
Dependent Claim
29 words
The method of claim 12 wherein said reordering step includes the step of accessing a memory having a look-up table for the association of input leads to output leads.
Claim 16
Dependent Claim
23 words
The method of claim 12 wherein said reordering step comprises the step of passing data from individual input leads to multiple output leads.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-02-14 | 1997-08-16 | 1998-02-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-14 | 2001-08-16 | 2002-02-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-14 | 2005-08-16 | 2006-02-15 | $7700.00 | Window Closed / Lapsed |