Data detecting apparatus using an over sampling and an interpolation means

Claim 2

A data detecting apparatus for detecting data in a digital signal obtained via a channel, said digital signal having data generated at a rate of fs, comprising: first sampling means for sampling said digital signal and for generating a succession of samples, said first sampling means comprising means for performing zero-filled over-sampling at a rate of 2 NPLL-1 ·fs, NPLL-1 being a number that is one less than a word length in bits of said samples; interpolating means following said first sampling means for interpolating signal values between said samples generated by said first sampling means and thereby generating a plurality of interpolated signals each having a phase, said interpolating means comprising a finite impulse response filter that operates at said rate of 2 NPLL-1 ·fs; phase-locked loop means for generating a signal identifying a selected phase; and second sampling means following said interpolating means for identifying and extracting interpolated signals from among said plurality of interpolated signals which are correlated to said selected phase.

Claim 3

A data detecting apparatus according to claim 1, further comprising detecting means for detecting data from said interpolated signal values extracted by said second sampling means.

Claim 4

A data detecting apparatus according to claim 2, wherein said data detecting means comprises a Viterbi decoding means for performing maximum likelihood decoding.

Claim 5

A data detecting apparatus according to claim 2, further comprising: analog-to-digital converting means for generating said digital signal from an analog signal; and an equalizing means disposed between said analog-to-digital converter and said interpolating means for equalizing said digital signal generated by said analog-to-digital converting means; wherein said analog-to-digital converting means, said equalizing means, said first sampling means, and said detecting means all operate in synchronization with a common clock having a fixed frequency.

Claim 6

A data detecting apparatus according to claim 1, wherein said phase-locked loop means comprises means for generating phase information from said digital signal for setting said selected phase as a zero-degree phase data presence point.

Claim 7

A data detecting apparatus as claimed in claim 1, wherein said interpolating means comprises: a plurality of successive stages, including a fist stage supplied with said succession of samples, a second stage, a plurality of successive stages following said second stage, and a last stage, each stage including a read-only-memory in which coefficients are stored; selector means connected to each read-only-memory for causing each read-only memory to emit one of the coefficients stored therein, dependent on said selected phase; said first stage having multiplier means for multiplying an incoming sample in said succession of samples by the coefficient emitted by the read-only-memory in said first stage, to generate a product; said second stage having delay means for delaying said incoming sample to produce a delayed sample, multiplier means for multiplying said delayed sample by the coefficient emitted by the read-only-memory in said second stage to generate a product, and adder means for generating a sum by adding the product generated in said second stage to the product generated by said first stage; and each of said successive stages having delay means for delaying the delayed sample from an immediately preceding stage to produce a new delayed sample, multiplier means for multiplying said new delayed sample by the coefficient emitted by the read-only-memory in that stage to generate a product, and adder means for generating a sum by adding the product generated in that stage to the sum generated in said immediately preceding stage, with the sum generated in said last stage comprising an interpolated signal.