US5061925A
Expired / Lapsed
US
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Phase equalization system for a digital-to-analog converter utilizing separate digital and analog sections
Assignee: Cirrus Logic Inc
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Filing: 1990-08-22
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Granted: 1991-10-29
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Expires: 2010-08-22
Abstract
Abstract A phase equalization system for a digital-to-analog converter (DAC) includes a digital portion (10) having an interpolation section (14) for receiving a digital input and increasing the sampling frequency thereof for input to a delta-sigma modulator (16). A summing junction (24) is disposed between the interpolation circuit (14) and the delta-sigma modudlator (16) to allow an offset voltage to be summed therewith. This provides for D.C. offset, this offset being controlled by a calibration control (40). The output of the digital section (10) is input in an analog section (12), which has a one-bit DAC 21) that is input to an analog filter (22) for converting and filtering the one-bit digital stream output by the delta-sigma modulator (16). The interpolation circuit (14) includes a three stage interpolation filter comprising a first stage (50), a second stage (52) and a third stage (54). The second stage (52) is comprised of a finite impulse response filter (FIR) that has a nonlinear phase response. The nonlinear phase response of the interpolation filter (52) compensates for the phase deviation of the analog filter (22) from a linear phase response. Therefore, the composite phase provided by the combination of the phase equalization in the digital section (10) and the phase nonlinearity in the analog section (12) will result in a linear overall phase relationship for the DAC.
Inventors
- 👤 Navdeep S. Sooch
- 👤 Donald A. Kerth
- 👤 Eric J. Swanson
- 👤 Tetsurou Sugimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 23:29
CPC Classifications
H; H03; H03M; H03M3/00; H03M3/30; H03M3/322; H03M3/368; H03M3/37; H03M3/50; H03M7/00; H03M7/30; H03M7/3002; H03M7/3004; H03M7/3015; H03M7/302; H03M7/3024; H03M7/3028; H03M7/3031; H03M7/3033; H03M7/3035; H03M7/3037
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
165 words
A digital-to-analog converter with linear phase, comprising: a digital input terminal; an analog output terminal; a digital processing section for conditioning a digital input signal received on said digital input terminal to provide a conditioned digital output signal, said digital processing section having a predetermined phase response; an analog section having a predetermined phase response over the passband of said analog section for receiving the output of said digital processing section, converting the conditioned digital output signal to an analog signal and filtering out images and quantization noise generated by said digital processing section that are outside the passband of said analog section; and a phase equalizer operating in the digital domain and associated with said digital processing section for adjusting the phase response of said digital processing section to compensate for variations from a linear phase response of the phase response of said analog section to provide a substantially linear phase response for the combination of said digital processing section and said analog section.
Claim 2
Dependent Claim
165 words
A digital-to-analog converter with linear phase, comprising: a digital input terminal; an analog output terminal; a digital processing section for conditioning a digital input signal received on said digital input terminal to provide a conditioned digital output signal, said digital processing section having a predetermined phase response; an analog section having a predetermined phase response over the passband of said analog section for receiving the output of said digital processing section, converting the conditioned digital output signal to an analog signal and filtering out images and quantization noise generated by said digital processing section that are outside the passband of said analog section; and a phase equalizer operating in the digital domain and associated with said digital processing section for adjusting the phase response of said digital processing section to compensate for variations from a linear phase response of the phase response of said analog section to provide a substantially linear phase response for the combination of said digital processing section and said analog section.
Claim 3
Dependent Claim
16 words
The digital-to-analog converter of claim 1, wherein said analog section comprises an analog low pass filter.
Claim 4
Dependent Claim
70 words
The digital-to-analog converter of claim 1, wherein said digital processing section comprises: an interpolation filter for receiving said digital input signal and increasing the sampling frequency thereof; an n-bit quantizer for receiving the output of said interpolation filter and outputting a n-bit digital stream for input to said analog section; and said analog section including a n-bit digital-to-analog convertor to convert the one bit digital stream to a converted signal.
Claim 5
Dependent Claim
14 words
The digital-to-analog converter of claim 3, wherein said n-bit quantizer comprises a delta-sigma modulator.
Claim 6
Dependent Claim
17 words
The digital-to-analog converter of claim 3, wherein said interpolation filter comprises a finite impulse response filter function.
Claim 7
Dependent Claim
46 words
The digital-to-analog converter of claim 3, wherein said interpolation filter includes means for adjusting the phase of said interpolation filter to comprise said phase equalizer and to provide said compensation for the variations from a linear phase response of the phase response of said analog section.
Claim 8
Independent Claim
136 words
A method for linearizing the phase response of a digital-to-analog converter comprising: receiving a digital input signal on a digital input; processing a digital signal to condition the digital input signal to provide a conditioned digital output signal; converting the conditioned digital output signal to an analog signal; filtering the analog signal in the analog domain over a predetermined passband to filter out images and quantization noise that occur outside of the passband to provide an analog output signal on an analog output; and adjusting the phase response in the digital domain to compensate for variations from a linear phase response of the filtering step in the analog domain; wherein a substantially linear phase response is provided for the combined operation of converting the digital signal to an analog signal and filtering in the analog domain.
Claim 9
Independent Claim
136 words
A method for linearizing the phase response of a digital-to-analog converter comprising: receiving a digital input signal on a digital input; processing a digital signal to condition the digital input signal to provide a conditioned digital output signal; converting the conditioned digital output signal to an analog signal; filtering the analog signal in the analog domain over a predetermined passband to filter out images and quantization noise that occur outside of the passband to provide an analog output signal on an analog output; and adjusting the phase response in the digital domain to compensate for variations from a linear phase response of the filtering step in the analog domain; wherein a substantially linear phase response is provided for the combined operation of converting the digital signal to an analog signal and filtering in the analog domain.
Claim 10
Dependent Claim
26 words
The method of claim 7, wherein the step of filtering comprises processing the analog signal output by the step of converting with a low pass filter.
Claim 11
Dependent Claim
62 words
The method of claim 7, wherein the step of processing the digital input signal in the digital domain and converting it to an analog signal comprises: providing an interpolation filter; processing the digital signal through the interpolation filter to increase the sampling frequency thereof; and converting the digital input signal in the digital domain to a n-bit stream with a n-bit quantizer.
Claim 12
Dependent Claim
37 words
The method of claim 9, wherein the step of converting the digital signal output by the interpolation filter to a n-bit digital stream comprises processing the digital signal output by the interpolation filter through a delta-sigma modulator.
Claim 13
Dependent Claim
16 words
The method of claim 9, wherein the interpolation filter has a finite impulse response filter function.
Claim 14
Dependent Claim
24 words
The method of claim 9, wherein the step of equalizing the phase comprises adjusting the phase of the phase response of the interpolation filter.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-10-28 | 1995-04-29 | 1995-10-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-10-28 | 1999-04-29 | 1999-10-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-10-28 | 2003-04-29 | 2003-10-29 | $7700.00 | Window Closed / Lapsed |