US5481500A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Precharged bit decoder and sense amplifier with integrated latch usable in pipelined memories
Assignee: International Business Machines Corp
•
Filing: 1994-07-22
•
Granted: 1996-01-02
•
Expires: 2014-07-22
Abstract
Abstract A memory and sense amplifier with latched output included therein derives high speed and noise immunity with precharged logic circuits through the separation of sense amplifier enablement and resetting by use of the precharge operation. Inclusion of bit line decoders which are wholly or partially self-resetting and self-precharging in sense amplifier support circuitry allows high performance at extremely short memory operation cycle times. A multiplexor is included which is usable in operating cycles as well as test cycles of the memory and further, in combination with other elements of the memory and sense amplifier arrangement, enables the pipelining of plural memory operations in a single memory cycle.
Inventors
- 👤 William R. Reohr
- 👤 Yuen H. Chan
- 👤 Pong-Fei Lu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:57
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/10; G11C7/00; G11C7/06; G11C7/065
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
78 words
A precharged sense amplifier arrangement including a bistable differential amplifier, means for enabling sensing of a differential voltage by said bistable differential amplifier, said means for enabling sensing including a means for causing latching of outputs of said differential amplifier, and means for precharging at least said means for enabling sensing and inputs of said differential amplifier in sequence, said means for precharging including means for resetting said means for causing latching of outputs of said differential amplifier.
Claim 2
Dependent Claim
78 words
A precharged sense amplifier arrangement including a bistable differential amplifier, means for enabling sensing of a differential voltage by said bistable differential amplifier, said means for enabling sensing including a means for causing latching of outputs of said differential amplifier, and means for precharging at least said means for enabling sensing and inputs of said differential amplifier in sequence, said means for precharging including means for resetting said means for causing latching of outputs of said differential amplifier.
Claim 3
Dependent Claim
18 words
A sense amplifier as recited in claim 1 wherein said means for enabling sensing includes a dual-slope circuit.
Claim 4
Dependent Claim
26 words
A sense amplifier as recited in claim 2 wherein said means for causing latching comprises a latch circuit connected to a portion of said dual-slope circuit.
Claim 5
Independent Claim
96 words
A method of operating a memory device including at least two sense amplifiers, each of said at least two sense amplifiers including means for precharging a respective one of said sense amplifiers in response to a precharge signal, said method including the steps of performing a read operation concurrently with said at least two sense amplifiers, interrupting a precharge signal to at least one of said at least two sense amplifiers, and performing a further read operation with at least another of said at least two sense amplifiers in the same cycle as said interrupting step.
Claim 6
Independent Claim
96 words
A method of operating a memory device including at least two sense amplifiers, each of said at least two sense amplifiers including means for precharging a respective one of said sense amplifiers in response to a precharge signal, said method including the steps of performing a read operation concurrently with said at least two sense amplifiers, interrupting a precharge signal to at least one of said at least two sense amplifiers, and performing a further read operation with at least another of said at least two sense amplifiers in the same cycle as said interrupting step.
References Cited (Backward Citations)
US3983412A
Cited
US4045785A
Cited
US4253163A
Cited
USRE34026E
Cited
US4843595A
Cited
US5127739A
Cited
US4843264A
Cited
US4922461A
Cited
US4932002A
Cited
US5015891A
Cited
US5126974A
Cited
US5007024A
Cited
US5305272A
Cited
US5034636A
Cited
US5204560A
Cited
US5247479A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-01 | 1999-07-03 | 2000-01-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-01 | 2003-07-03 | 2004-01-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-01 | 2007-07-03 | 2008-01-02 | $7700.00 | Window Closed / Lapsed |