Sense amplifier for static memory device

Claim 1

In a MOSFET memory device comprising an array of static memory cells each connected to one of a series of address lines into a pair of complementary bit lines comprising one of a series of bit columns, pullup means connected from a voltage supply to each said bit line for applying a uniform bias voltage, and column select means for each column for providing a voltage to select said column, a sense-amplifier for each bit column connected to complementary output bus lines which are connected through a pair of load elements to said voltage supply and comprising: a pair of MOSFET signal transistors each having a drain connected to a said output bus line, a source connected to a voltage return, and an insulated gate; a voltage translator section connected to said bit lines of the bit column and to said gates of said signal transistors for shifting the relatively high voltage levels of said bit lines, which includes said uniform bias, to a voltage level close to the threshold of said signal transistors; said translator comprising a pair of networks connected to a voltage supply, each said network having a first MOSFET transistor and a second MOSFET transistor connected in series with the source of said first transistor connected to said voltage return and the drain of said second transistor connected to said column select means; the gate of the first transistor of said first network and the gate of the second transistor of said second network being together connected to one of the bit lines of said column; the gate of one of said signal transistors being connected to a node between the first and second transistor of said first network and the gate of the other of said signal transistors being connected to a node between the first and second transistors of said second network.