Sense amplifier with an integral logic function

Claim 2

A sense amplifier with an integral logic function, comprising: input means, for providing a first difference signal in response to detecting a difference between a first input signal and a second input signal when a control signal coupled thereto is in a predetermined logic state, and for providing a second difference signal in response to detecting a difference between said second input signal and said first input signal when a complement of said control signal is in said predetermined logic state; output means coupled to said input means, for providing an output signal in response to said first difference signal or said second difference signal; and enabling means coupled to said input means, for enabling the sense amplifier in response to a select signal, comprising: a first transistor having a first current electrode coupled to said first difference signal, a control electrode for receiving said select signal, and a second current electrode coupled to said second difference signal; and a second transistor having a first current electrode coupled to said input means, a control electrode for receiving said select signal, and a second current electrode coupled to a first power supply voltage terminal.

Claim 3

The sense amplifier of claim 1 wherein said input means comprises: a third transistor having a first current electrode coupled to a second power supply voltage terminal, a control electrode, and a second current electrode for providing said first difference signal; a fourth transistor having a first current electrode coupled to said second power supply voltage terminal, a control electrode coupled to said control electrode of said third transistor, and a second current electrode for providing said second difference signal; a fifth transistor having a first current electrode coupled to said second current electrode of said third transistor, a control electrode for receiving said control signal, and a second current electrode coupled to said control electrode of said third transistor; a sixth transistor having a first current electrode coupled to said second current electrode of said fourth transistor, a control electrode for receiving said complement of said control signal, and a second current electrode coupled to said control electrode of said third transistor; a seventh transistor having a first current electrode coupled to said second current electrode of said third transistor, a control electrode for receiving said second input signal, and a second current electrode coupled to said first current electrode of said second transistor; and an eighth transistor having a first current electrode coupled to said second current electrode of said fourth transistor, a control electrode for receiving said first input signal, and a second current electrode coupled to said first current electrode of said second transistor.

Claim 4

The sense amplifier of claim 2 wherein said output means comprises: a first inverter having an input terminal coupled to said second current electrode of said third transistor, a positive enable input terminal for receiving said control signal, a negative enable input terminal for receiving said complement of said control signal, and an output terminal for providing said output signal; and a second inverter having an input terminal coupled to said second current electrode of said fourth transistor, a positive enable input terminal for receiving said complement of said control signal, a negative enable input terminal for receiving said control signal, and an output terminal coupled to said output terminal of said first inverter.

Claim 5

In a data processor having means for storing data, a circuit comprising: first and second input transistors respectively having first current electrodes coupled to a virtual ground node, and respectively receiving first and second signals on control electrodes thereof; a third transistor having a first current electrode coupled to a second current electrode of said first transistor, a control electrode, and a second current electrode coupled to a positive power supply voltage terminal; a fourth transistor having a first current electrode coupled to a second current electrode of said second transistor, a control electrode coupled to said control electrode of said third transistor, and a second current electrode coupled to said positive power supply voltage terminal; and logic means coupled to said first, second, third, and fourth transistors, for coupling together said control electrode and said first current electrode of said third transistor in response to a complement of a control signal, and for coupling together said control electrode and said first current electrode of said fourth transistor in response to said control signal.

Claim 6

In a data processor having means for storing data, a circuit comprising: first and second input transistors respectively having first current electrodes coupled to a virtual ground node, and respectively receiving first and second signals on control electrodes thereof; a third transistor having a first current electrode coupled to a second current electrode of said first transistor, a control electrode, and a second current electrode coupled to a positive power supply voltage terminal; a fourth transistor having a first current electrode coupled to a second current electrode of said second transistor, a control electrode coupled to said control electrode of said third transistor, and a second current electrode coupled to said positive power supply voltage terminal; and logic means coupled to said first, second, third, and fourth transistors, for coupling together said control electrode and said first current electrode of said third transistor in response to a complement of a control signal, and for coupling together said control electrode and said first current electrode of said fourth transistor in response to said control signal.

Claim 7

The circuit of claim 4 further comprising output means, said output means for providing said output signal either from said voltage on said second current electrode of said first transistor in response to a complement of a third signal, or from said voltage on said second current electrode of said second transistor in response to said third signal.

Claim 8

The circuit of claim 5 wherein said third signal is equal to said control signal.

Claim 9

In a data processor having means for storing data, a method of simultaneously performing a logic function and a compare operation in a single circuit comprising the steps of: enabling the circuit for operation; making conductive either a first input transistor receiving a first input signal, or a a second input transistor receiving a second input signal, first current electrodes of said first and second transistors each coupled to a negative power supply voltage terminal when the circuit is enabled; selectively coupling second current electrodes of said first and second input transistors substantially to a positive power supply voltage terminal in response to first and second control signals, respectively; and providing an output signal either in response to a difference between said first input signal and said second input signal if said first control signal assumes a predetermined logic state, or in response to a difference between said second input signal and said first input signal if said second control signal assumes said predetermined logic state.

Claim 10

In a data processor having means for storing data, a method of simultaneously performing a logic function and a compare operation in a single circuit comprising the steps of: enabling the circuit for operation; making conductive either a first input transistor receiving a first input signal, or a a second input transistor receiving a second input signal, first current electrodes of said first and second transistors each coupled to a negative power supply voltage terminal when the circuit is enabled; selectively coupling second current electrodes of said first and second input transistors substantially to a positive power supply voltage terminal in response to first and second control signals, respectively; and providing an output signal either in response to a difference between said first input signal and said second input signal if said first control signal assumes a predetermined logic state, or in response to a difference between said second input signal and said first input signal if said second control signal assumes said predetermined logic state.

Claim 11

A sense amplifier with an integral logic function, comprising: first and second transistors each having a first current electrode coupled to a virtual ground node, and a control electrode for receiving first and second signals, respectively, each transistor having a second current electrode respectively coupled to first and second nodes; and means coupled to said second current electrodes of said first and second transistors, for selectively mirroring either a current conducted through said second transistor into said first node, or a current conducted through said first transistor into said second node, respectively in response to a control signal and a complement of said control signal.

Claim 12

A sense amplifier with an integral logic function, comprising: first and second transistors each having a first current electrode coupled to a virtual ground node, and a control electrode for receiving first and second signals, respectively, each transistor having a second current electrode respectively coupled to first and second nodes; and means coupled to said second current electrodes of said first and second transistors, for selectively mirroring either a current conducted through said second transistor into said first node, or a current conducted through said first transistor into said second node, respectively in response to a control signal and a complement of said control signal.

Claim 13

The sense amplifier of claim 8 wherein said means comprises: a third transistor having a first current electrode coupled to a power supply voltage terminal, a control electrode, and a second current electrode coupled to said second current electrode of said first transistor; a fourth transistor having a first current electrode coupled to said power supply voltage terminal, a control electrode coupled to said control electrode of said third transistor, and a second current electrode coupled to said second current electrode of said second transistor; a fifth transistor having a first current electrode coupled to said control electrodes of said third and fourth transistors, a control electrode for receiving said complement of said control signal, and a second current electrode coupled to said second current electrode of said third transistor; and a sixth transistor having a first current electrode coupled to said control electrodes of said third and fourth transistors, a control electrode for receiving said control signal, and a second current electrode coupled to said second current electrode of said fourth transistor.

Claim 14

The sense amplifier of claim 8 further comprising enabling means coupled to said first and second transistors, for enabling the sense amplifier in response to a select signal.

Claim 15

The sense amplifier of claim 10 wherein said enabling means comprises: a seventh transistor having a first current electrode coupled to said second current electrode of said first transistor, a control electrode for receiving said select signal, and a second current electrode coupled to said second current electrode of said second transistor; and an eighth transistor having a first current electrode coupled to said first current electrodes of said first and second transistors at said virtual ground, a control electrode for receiving said select signal, and a second current electrode coupled to a second power supply voltage terminal.

Claim 16

The sense amplifier of claim 8 further comprising output means coupled to said first and second nodes, for providing an output signal in response to either a voltage at said second node if said control signal is active, or a voltage at said first node if said control signal is inactive.

Claim 17

The sense amplifier of claim 12 wherein said output means comprises: a first inverter having an input terminal coupled to said first node, a positive enable input terminal for receiving said complement of said control signal, a negative enable input terminal for receiving said control signal, and an output terminal for providing said output signal; and a second inverter having an input terminal coupled to said second node, a positive enable input terminal for receiving said control signal, a negative enable input terminal for receiving said complement of said control signal, and an output terminal coupled to said output terminal of said first inverter.