Semiconductor memory device with bit line sense amplifiers

Claim 1

A semiconductor memory comprising: a plurality of word lines; a plurality of pairs of bit lines with a folded bit line structure, each one of said pair of bit lines divided into a plurality of blocks, and each bit line of a pair of bit lines forming divided bit lines; a plurality of memory cells each connected to a corresponding word line of said plurality of word lines and a corresponding divided bit line of said plurality of pairs of bit lines; a plurality of sense amplifiers provided for each of the pairs of bit lines divided into said plurality of blocks for detecting and amplifying a difference between signal levels on the corresponding pair of divided bit lines after a particular word line is selected from said plurality of word lines; a plurality of restore circuit provided for each of the pairs of bit lines divided into said plurality of blocks for detecting and further amplifying said difference between signal levels amplified by said sense amplifiers on a corresponding pair of divided bit lines; first switching means provided for each of said divided bit lines for electrically connecting adjacent divided bit lines to each other; a control circuit for generating activating signals for sequentially activating said plurality of restore circuits in a predetermined order beginning at a restore circuit provided in a block including said selected word line; and switch control means responsive to said activating signals for controlling an operation of said first switching means, said switch control means responsive to one of said activating signals to render said first switching means conductive.