Method and apparatus for obtaining data from a data circuit utilizing alternating clock pulses to gate the data to the output

Claim 3

The apparatus according to claim 1 wherein the data circuit comprises a random access memory.

Claim 4

The apparatus according to claim 1 wherein the data circuit propagates the clock signal through a plurality of levels of logic to generate the selected delay.

Claim 5

The apparatus according to claim 1 wherein the signal storing means comprises: a first delay element coupled to the clock signal receiving means for producing a first delayed clock signal in response to the first clock signal, the first delay element having a delay less than the selected delay; a second delay element coupled to the clock signal receiving means for producing a second delayed clock signal in response to the second clock signal, the second delay element having a delay less than the selected delay; wherein the first data signal is stored in one of the first memory element or second memory element in response to the first delayed clock signal, and the second data signal is stored in the other first memory element or second memory element in response to the second delayed clock signal.

Claim 6

The apparatus according to claim 4 wherein the data circuit propagates the clock signal through a plurality of levels of post-charge inverter logic to generate the selected delay.

Claim 7

The apparatus according to claim 5 wherein the first delay element comprises a plurality of levels of post-charge inverter logic, and wherein the second delay element comprises a plurality of levels of post-charge inverter logic.

Claim 8

The apparatus according to claim 4 wherein the signal storing means further comprises: a bistable element coupled to the first delay element and to the second delay element for generating a first bistable signal in response to the first delayed clock signal and for producing a second bistable signal in response to the second delayed clock signal; and gate means, coupled to the bistable element, to the data circuit, to the first memory element, and to the second memory element, for storing the first data signal in the first memory element in response to the first bistable signal and for storing the second data signal in the second memory element in response to the second bistable signal.

Claim 9

The apparatus according to claim 7 wherein the bistable element comprises a flip-flop.

Claim 10

The apparatus according to claim 8 wherein the first memory element comprises a first flip-flop, and wherein the second memory element comprises a second flip-flop.

Claim 11

The apparatus according to claim 9 wherein the gate means comprises: a first AND gate having a first input terminal coupled to the output node, a second input terminal coupled to the bistable element for receiving the first bistable signal therefrom, and an output terminal coupled to the first flip-flop; and a second AND gate having a first input terminal coupled to the first output node, a second input terminal coupled to the bistable element for receiving the second bistable signal therefrom, and an output terminal coupled to the second flip-flop.

Claim 12

In a data processing system including a random access memory, a master clock, and a data clock, wherein the master clock generates master clock pulses having a selected frequency, each master clock pulse having a leading edge and a trailing edge, wherein the data clock generates a first data clock signal corresponding to the leading edge of each master clock pulse for accessing the memory and a second data clock signal corresponding to the trailing edge of each master clock pulse for accessing the memory, wherein the memory produces a first data signal on the output node in response to the first data clock signal and a second data signal on the output node in response to the second data clock signal, and wherein the memory has a selected delay between the time a data clock signal initiates access of the memory and the time the data appears at the output node, an apparatus for retrieving data from the memory comprising: a first memory element for storing data signals from the output node; a second memory element for storing data signals from the output node; and signal storing means having means for producing first and second delayed data clock signals that have a delay less than the selected delay of the memory, coupled to the memory, to the first memory element, and to the second memory element, for storing the first data signal in one of the first memory element or second memory element in response to the first delayed data clock signal and for storing the second data signal in the other first memory element or second memory element in response to the second delayed data clock signal.

Claim 13

In a data processing system including a random access memory, a master clock, and a data clock, wherein the master clock generates master clock pulses having a selected frequency, each master clock pulse having a leading edge and a trailing edge, wherein the data clock generates a first data clock signal corresponding to the leading edge of each master clock pulse for accessing the memory and a second data clock signal corresponding to the trailing edge of each master clock pulse for accessing the memory, wherein the memory produces a first data signal on the output node in response to the first data clock signal and a second data signal on the output node in response to the second data clock signal, and wherein the memory has a selected delay between the time a data clock signal initiates access of the memory and the time the data appears at the output node, an apparatus for retrieving data from the memory comprising: a first memory element for storing data signals from the output node; a second memory element for storing data signals from the output node; and signal storing means having means for producing first and second delayed data clock signals that have a delay less than the selected delay of the memory, coupled to the memory, to the first memory element, and to the second memory element, for storing the first data signal in one of the first memory element or second memory element in response to the first delayed data clock signal and for storing the second data signal in the other first memory element or second memory element in response to the second delayed data clock signal.

Claim 14

The apparatus according to claim 11 wherein the signal storing means comprises: a first delay element coupled to the data clock for producing a first delayed data clock signal in response to the first data clock signal corresponding to the leading edge, the first delay element having a delay less than the selected delay; a second delay element coupled to the data clock for producing a second delayed data clock signal in response to the second data clock signal corresponding to the leading edge, the second delay element having a delay less than the selected delay; wherein the first data signals are stored in one of the first memory element or second memory element in response to the first delayed data clock signal, and the second data signals are stored in the other first memory element or second memory element in response to the second delayed data clock signal.

Claim 15

The apparatus according to claim 12 wherein the signal storing means further comprises: a bistable element coupled to the first delay element and to the second delay element for generating a first bistable signal in response to the first delayed data clock signal and for producing a second bistable signal in response to the second delayed data clock signal; and gate means, coupled to the bistable element, to the memory, to the first memory element, and to the second memory element, for storing the first data signals in the first memory element in response to the first bistable signal and for storing the second data signals in the second memory element in response to the second bistable signal.

Claim 16

The apparatus according to claim 13 wherein the bistable element comprises a bistable flip-flop having a first input terminal coupled to the first delay element and a second input terminal coupled to the second delay element.

Claim 17

The apparatus according to claim 14 wherein the first memory element comprises a first flip-flop, and wherein the second memory element comprises a second flip-flop.

Claim 18

The apparatus according to claim 15 wherein the gate means comprises: a first AND gate having a first input terminal coupled to the output node, a second input terminal coupled to the bistable element for receiving the first bistable signal therefrom, and an output terminal coupled to the first flip-flop, and a second AND gate having a first input terminal coupled to the output node, a second input terminal coupled to the bistable element for receiving the second bistable signal therefrom, and an output terminal coupled to the second flip-flop.

Claim 19

The apparatus according to claim 16 wherein the memory propagates the clock signal through a plurality of levels of post-charge inverter logic to generate the selected delay.

Claim 20

The apparatus according to claim 17 wherein the first delay element comprises a plurality of levels of post-charge inverter logic, and wherein the second delay element comprises a plurality of levels of post-charge inverter logic.

Claim 23

The apparatus according to claim 19 wherein the signal storing means comprises: a first delay element coupled to the data clock means for producing a first delayed data clock signal in response to the first data clock pulse, the first delay element having a delay less than the selected delay; a second delay element coupled to the data clock means for producing a second delayed data clock signal in response to the second data clock pulse, the second delay element having a delay less than the selected delay; wherein the first data signal is stored in one of the first memory element or second memory element in response to the first delayed data clock signal, and the second data signal is stored in the other first memory element or second memory element in response to the second delayed data clock signal.

Claim 24

The apparatus according to claim 20 wherein the signal storing means further comprises: a bistable element coupled to the first delay element and to the second delay element for generating a first bistable signal in response to the first delayed data clock signal and for producing a second bistable signal in response to the second delayed data clock signal; and gate means, coupled to the bistable element, to the data circuit, to the first memory element, and to the second memory element, for storing the first data signal in the first memory element in response to the first bistable signal and for storing the second data signal in the second memory element in response to the second bistable signal.

Claim 25

The apparatus according to claim 21 wherein the bistable element comprises a fistable flip-flop having a first input terminal coupled to the first delay element and a second input terminal coupled to the second delay element.

Claim 26

The apparatus according to claim 22 wherein the first memory element comprises a first flip-flop, and wherein the second memory element comprises a second flip-flop.

Claim 27

The apparatus according to claim 23 wherein the gate means comprises: a first AND gate having a first input terminal coupled to the output node, a second input terminal coupled to the bistable element for receiving the first bistable signal therefrom, and an output terminal coupled to an input terminal of the first flip-flop; a second AND gate having a first input terminal coupled to the output node, a second input terminal coupled to the bistable element for receiving the second bistable signal therefrom, and an output terminal coupled to an input terminal of the second flip-flop.

Claim 28

The apparatus according to claim 24 wherein the data circuit comprises a random access memory.

Claim 29

The apparatus according to claim 25 wherein the data circuit propagates the clock signal through a plurality of levels of post-charge inverter logic to generate the selected delay.

Claim 30

The apparatus according to claim 26 wherein the first delay element comprises a plurality of levels of post-charge inverter logic, and wherein the second delay element comprises a plurality of levels of post-charge inverter logic.

Claim 31

In a memory system including a random access memory having a first output node which produces an active signal representing a selected data logic level and a second output node which produces an active signal representing a complementary data logic level, an apparatus for retrieving data from the memory comprising: master clock means for generating master clock pulses having a selected frequency, each clock pulse having a leading edge and a trailing edge; data clock means for generating a first data clock pulse corresponding to the leading edge of each master clock pulse, and for generating a second data clock pulse corresponding to the trailing edge of each master clock pulse; wherein the memory is coupled to the data clock means for receiving the data clock pulses therefrom; wherein the memory produces first data signals on the first and second output nodes in response to the first data clock pulse and second data signals on the first and second output nodes in response to the second data clock pulse; wherein the memory has a selected delay between the time a data clock pulse initiates access of the memory and the time the data appears at the first and second output nodes; a first memory element for storing data signals from the first and second output nodes; a second memory element for storing data signals from the first and second output nodes; and signal storing means, coupled to the memory, to the first memory element, and to the second memory element, for storing the first data signals in one of the first memory element or second memory element in response to the first data clock pulse and for storing the second data signals in the other first memory element or second memory element in response to the second data clock pulse.

Claim 32

In a memory system including a random access memory having a first output node which produces an active signal representing a selected data logic level and a second output node which produces an active signal representing a complementary data logic level, an apparatus for retrieving data from the memory comprising: master clock means for generating master clock pulses having a selected frequency, each clock pulse having a leading edge and a trailing edge; data clock means for generating a first data clock pulse corresponding to the leading edge of each master clock pulse, and for generating a second data clock pulse corresponding to the trailing edge of each master clock pulse; wherein the memory is coupled to the data clock means for receiving the data clock pulses therefrom; wherein the memory produces first data signals on the first and second output nodes in response to the first data clock pulse and second data signals on the first and second output nodes in response to the second data clock pulse; wherein the memory has a selected delay between the time a data clock pulse initiates access of the memory and the time the data appears at the first and second output nodes; a first memory element for storing data signals from the first and second output nodes; a second memory element for storing data signals from the first and second output nodes; and signal storing means, coupled to the memory, to the first memory element, and to the second memory element, for storing the first data signals in one of the first memory element or second memory element in response to the first data clock pulse and for storing the second data signals in the other first memory element or second memory element in response to the second data clock pulse.

Claim 33

The apparatus according to claim 28 wherein the signal storing means comprises: a first delay element coupled to the data clock for producing a first delayed data clock signal in response to the first data clock pulse, the first delay element having a delay less than the selected delay; a second delay element coupled to the data clock for producing a second delayed data clock signal in response to the second data clock pulse, the second delay element having a delay less than the selected delay; wherein the first data signals are stored in one of the first memory element or second memory element in response to the first delayed data clock signal, and the second data signals are stored in the other first memory element or second memory element in response to the second delayed data clock signal.

Claim 34

The apparatus according to claim 29 wherein the signal storing means further comprises: a bistable element coupled to the first delay element and to the second delay element for generating a first bistable signal in response to the first delayed data clock signal and for producing a second bistable signal in response to the second delayed data clock signal; and gate means, coupled to the bistable element, to the memory, to the first memory element, and to the second memory element, for storing the first data signals in the first memory element in response to the first bistable signal and for storing the second data signals in the second memory element in response to the second bistable signal.

Claim 35

The apparatus according to claim 30 wherein the bistable element comprises a bistable flip-flop having a first input terminal coupled to the first delay element and a second input terminal coupled to the second delay element.

Claim 36

The apparatus according to claim 31 wherein the first memory element comprises a first flip-flop, and wherein the second memory element comprises a second flip-flop.

Claim 37

The apparatus according to claim 32 wherein the gate means comprises: a first AND gate having a first input terminal coupled to the first output node, a second input terminal coupled to the bistable element for receiving the first bistable signal therefrom, and an output terminal coupled to a first input terminal of the first flip-flop; a second AND gate having a first input terminal coupled to the second output node, a second input terminal coupled to the bistable element for receiving the first bistable signal therefrom, and an output terminal coupled to a second input terminal of the first flip-flop; a third AND gate having a first input terminal coupled to the first output node, a second input terminal coupled to the bistable element for receiving the second bistable signal therefrom, and an output terminal coupled to a first input terminal of the second flip-flop; and a fourth AND gate having a first input terminal coupled to the second output node, a second input terminal coupled to the bistable element for receiving the second bistable signal therefrom, and an output terminal coupled to a second input terminal of the second flip-flop.

Claim 38

The apparatus according to claim 33 wherein the memory propagates the clock signal through a plurality of levels of post-charge inverter logic to generate the selected delay.

Claim 39

The apparatus according to claim 34 wherein the first delay element comprises a plurality of levels of post-charge inverter logic, and wherein the second delay element comprises a plurality of levels of post-charge inverter logic.

Claim 42

The method according to claim 36 further comprising the steps of: producing a first bistable signal in response to the first delayed clock signal for gating the first data signal to the first memory element; producing a second bistable signal in response to the second delayed clock signal for gating the second data signal to the second memory element; storing the first data signal in the first memory element in response to the first bistable signal; and storing the second data signal in the second memory element in response to the second bistable signal.

Claim 43

The method according to claim 37 further comprising the step of propagating the clock signal through a plurality of levels of post-charge inverter logic in the data circuit to generate the selected delay.

Claim 44

The method according to claim 38 wherein the step of propagating the first clock pulse through the first delay element comprises the step of propagating the first clock pulse through a plurality of levels of post-charge inverter logic, and wherein the step of propagating the second clock pulse through the second delay element comprises the step of propagating the second clock pulse through a plurality of levels of post-charge inverter logic.