US4056851A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Elastic buffer for serial data
Assignee: RCA Corp
•
Filing: 1976-09-20
•
Granted: 1977-11-01
•
Expires: 1996-09-20
Abstract
Abstract An elastic buffer, including a single random access memory, receives information bits at a rate determined by a receiving clock, and transmits the information bits at a rate determined by an output clock, where the clocks are not exactly synchronous. A read-write memory timing circuit synchronized by the output clock repeatedly produces a read pulse followed by first and a second spaced write pulses. In response to the read pulse, a bit is read out from the memory at an address determined by the contents of an address counter. In response to the first write pulse, a first received bit, if received, is written into the memory at an address determined by the contents of a read address counter. In response to the second write pulse, a second received bit, if received, is written into the memory at an address determined by the contents of the read address counter. An alarm is given if the numbers in the address counters are equal, indicating that the memory is empty, or filled and about to overflow.
Inventors
- 👤 Norman Hovagimyan
- 👤 John Michael Link
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 10:47
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F5/10; G06F5/12; G06F5/14; H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/062; H04J3/0626; H04L; H04L25/00; H04L25/02; H04L25/05
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
197 words
An elastic buffer for receiving information bits at a rate determined by a receiving clock, and transmitting the information bits at a rate determined by an output clock, where the clocks are not exactly synchronous, comprising a two-bit data input buffer, a random access memory, a read-write memory timing circuit synchronized by said output clock and repeatedly producing a read pulse followed by first and a second spaced write pulses, a read address counter and a write address counter, means responsive to said read pulse to read out a bit from said memory at an address determined by the contents of said read address counter, and then increment said counter, means responsive to said first write pulse and the presence of a first received bit in said two-bit buffer to write said bit into said memory at an address determined by the contents of said write address counter, and then increment said counter, and means responsive to said second write pulse and the presence of a second received bit in said two-bit buffer to write said bit into said memory at an address determined by the contents of said write address counter, and then increment said counter.
Claim 2
Dependent Claim
197 words
An elastic buffer for receiving information bits at a rate determined by a receiving clock, and transmitting the information bits at a rate determined by an output clock, where the clocks are not exactly synchronous, comprising a two-bit data input buffer, a random access memory, a read-write memory timing circuit synchronized by said output clock and repeatedly producing a read pulse followed by first and a second spaced write pulses, a read address counter and a write address counter, means responsive to said read pulse to read out a bit from said memory at an address determined by the contents of said read address counter, and then increment said counter, means responsive to said first write pulse and the presence of a first received bit in said two-bit buffer to write said bit into said memory at an address determined by the contents of said write address counter, and then increment said counter, and means responsive to said second write pulse and the presence of a second received bit in said two-bit buffer to write said bit into said memory at an address determined by the contents of said write address counter, and then increment said counter.
Claim 3
Dependent Claim
34 words
A buffer according to claim 1, and in addition, means to initialize said buffer comprising means for partially filling said memory with received information bits before starting to read information bits from the memory.
Claim 4
Dependent Claim
29 words
A buffer according to claim 1 and, in addition, means to fill said memory half full of received information bits before starting to read information bits from the memory.
Claim 5
Dependent Claim
78 words
A buffer according to claim 1, and in addition, sources of clock pulses at said transmitting and receiving rates, means to synchronize one of the memory read and write operations with a corresponding one of said transmitting and receiving clock pulses, and means operative during each of said operations to perform zero, one or two of the other of said memory read and write operations as required by the corresponding one of said transmitting and receiving clock pulses.
Claim 6
Dependent Claim
67 words
A buffer according to claim 1, and in addition, sources of clock pulses at said transmitting and receiving rates, means to synchronize each memory read operation with a corresponding transmitting clock pulse, and means operative between successive ones of said memory read operations to perform a number including zero of memory write operations determined by the number of receiving clock pulses occurring between successive transmitting clock pulses.
Claim 7
Dependent Claim
67 words
A buffer according to claim 1, and in addition, sources of clock pulses at said transmitting and receiving rates, means to synchronize each memory write operation with a corresponding receiving clock pulse, and means operative between successive ones of said memory write operations to perform a number including zero of memory read operations determined by the number of transmitting clock pulses occurring between successive receiving clock pulses.
References Cited (Backward Citations)
US3421147A
Cited
US3588840A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-10-31 | 1981-05-02 | 1981-11-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-10-31 | 1985-05-02 | 1985-11-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-10-31 | 1989-05-02 | 1989-11-01 | $7700.00 | Window Closed / Lapsed |