US3634869A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Interpulse time interval detection circuit
Assignee: Individual
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Filing: 1970-12-29
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Granted: 1972-01-11
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Expires: 1990-12-29
Abstract
Abstract Circuit for producing an output signal when a group of serial input signals, which are separated by decreasing intervals of time, are separated by a given interval of time. The input signals set a flip-flop which is reset by the input pulses delayed by the given interval of time. A second flip-flop producing the output signal is set by the input signals if the first flip-flop is set and is reset if the first flip-flop is reset.
Inventors
- 👤 Chia Ying Hsueh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 15:54
CPC Classifications
H; H03; H03K; H03K21/00
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
119 words
In a circuit for providing an indicative output signal when a group of serial input signals, which are separated by decreasing intervals of time, are separated by a given interval of time, the combination comprising: a first flip-flop; means responsive to the trailing edge of the input signals for setting the first flip-flop; delay means responsive to the input pulses for producing an output signal a given interval of time after each input pulse for resetting the first flip-flop; and a second flip-flop connected to be set by an input signal when the first flip-flop is set and to be reset by an input signal if the first flip-flop is reset, for producing the indicative output signal when set.
Claim 2
Dependent Claim
119 words
In a circuit for providing an indicative output signal when a group of serial input signals, which are separated by decreasing intervals of time, are separated by a given interval of time, the combination comprising: a first flip-flop; means responsive to the trailing edge of the input signals for setting the first flip-flop; delay means responsive to the input pulses for producing an output signal a given interval of time after each input pulse for resetting the first flip-flop; and a second flip-flop connected to be set by an input signal when the first flip-flop is set and to be reset by an input signal if the first flip-flop is reset, for producing the indicative output signal when set.
Claim 3
Dependent Claim
29 words
The invention as set forth in claim 1 wherein said second-stated means comprises a delay means having a delay interval equal to the time duration of said input signals.
Claim 4
Dependent Claim
20 words
The invention as set forth in claim 2 wherein said delay means is comprised of the leading edge delay circuit.
Claim 5
Dependent Claim
25 words
The invention as set forth in claim 3 wherein said first flip-flop is an S-R flip-flop and said second flip-flop is a clocked J-K flip-flop.
Claim 6
Dependent Claim
16 words
The invention as set forth in claim 4 wherein said second flip-flop is a D-type flip-flop.
Claim 7
Dependent Claim
41 words
The invention as set forth in claim 5 including a coincidence gate responsive to the input signals and the output of the second flip-flop for producing output signals when input signals occur and the second flip-flop is in the set state.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-01-10 | 1975-07-12 | 1976-01-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-01-10 | 1979-07-12 | 1980-01-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-01-10 | 1983-07-12 | 1984-01-11 | $7700.00 | Window Closed / Lapsed |