Memory access system including a memory controller with memory redrive circuitry

Claim 1

A memory access system, comprising: a. memory means for storing data, said memory means having a plurality of storage locations, each of said location being specified by a row and column address; b. a memory controller for performing a macro operation, said memory controller receiving a first row address of said row address and a first column address of said column address and executing a predetermined plurality of commands utilizing said first row address and column address, wherein said first row address and said first column address are reused during the macro operation for commands subsequent to a first command of said plurality of commands; wherein each of said commands including a command code, and said macro operation including a macro code; and said plurality of commands including fetch and store commands to fetch and store data to and from said memory means: said memory controller comprising: 1) a system timing unit for controlling the system timing; 2) a row and column address strobes generating means, coupled to the system timing unit, for generating a row address strobe (RAS) and a column address strobe (CAS), using said first row address and first column address; 3) special code detector, coupled to said system timing unit, for loading a predetermined count into said system timing means, when a predetermined condition exists. as determined by said special code detector; said system timing unit starts counting at said predetermined count and whereby said RAS is immediately activated, wherein said predetermined condition is when a command code match said macro code.