Graphics processor with staggered memory timing

Claim 3

The apparatus of claim 1, wherein said data bus is a bidirectional data bus.

Claim 4

The apparatus of claim 2, wherein said processor provides a write enable signal coupled to all of said memories for writing data into said memories.

Claim 5

The apparatus of claim 3, wherein said processor provides a separate output enable signal to each of said memories, wherein activation of each of said separate output enable signals in a staggered fashion causes data to be read from its corresponding memory so that data can be read from said memories in a staggered fashion.

Claim 6

The apparatus of claim 3, further including a data switcher coupled onto said data bus for distributing said data to each memory, such that data is written to each memory at different time periods.

Claim 7

The apparatus of claim 5, wherein said data switcher controls direction of data transfer between said processor and said memories and wherein a direction control signal is provided by said processor to said data switcher for controlling direction of said data transfer.

Claim 8

The apparatus of claim 6, further including an address switcher coupled onto said address bus for distributing said addresses to each memory at different time periods.

Claim 9

The apparatus of claim 4, wherein said memories are random-access-memories.

Claim 10

The apparatus of claim 4, wherein said memories are dynamic-random-access memories.

Claim 11

In a graphics display system having a host processor which provides instructions for providing an image to be displayed, an apparatus for providing pixel information for a raster scan display having pixels arranged in a plurality of horizontal lines to form said raster scan display, comprising: a plurality of memories accessed by row address data and column address data within a memory cycle; a graphics processor coupled to said memories; an address bus coupled to said graphics processor and said memories for coupling said row address data and said column address data from said graphics processor to said memories for accessing locations in said memories; a data bus coupled to said graphics processor and said memories for coupling data between said graphics processor and said memories; said graphics processor providing a separate row address strobe (RAS) signal and a separate column address strobe (CAS) signal to each of said memories, each of said RAS signals and each of said CAS signals being independently provided by said graphics processor and independently coupled to said memories; all of said RAS signals individually capable of having associated row address data which is unique from all other row address data associated with other RAS signals within said memory cycle and all of said CAS signals individually capable of having associated data which is unique from all other data associated with other CAS signals within said memory cycle; wherein staggering the strobing of either said RAS or CAS signals causes said memories to be accessed in a staggered fashion to transfer data between said graphics processor and said memories, such that overall data transfer rate is faster than said memory cycle of one of said memories.

Claim 12

In a graphics display system having a host processor which provides instructions for providing an image to be displayed, an apparatus for providing pixel information for a raster scan display having pixels arranged in a plurality of horizontal lines to form said raster scan display, comprising: a plurality of memories accessed by row address data and column address data within a memory cycle; a graphics processor coupled to said memories; an address bus coupled to said graphics processor and said memories for coupling said row address data and said column address data from said graphics processor to said memories for accessing locations in said memories; a data bus coupled to said graphics processor and said memories for coupling data between said graphics processor and said memories; said graphics processor providing a separate row address strobe (RAS) signal and a separate column address strobe (CAS) signal to each of said memories, each of said RAS signals and each of said CAS signals being independently provided by said graphics processor and independently coupled to said memories; all of said RAS signals individually capable of having associated row address data which is unique from all other row address data associated with other RAS signals within said memory cycle and all of said CAS signals individually capable of having associated data which is unique from all other data associated with other CAS signals within said memory cycle; wherein staggering the strobing of either said RAS or CAS signals causes said memories to be accessed in a staggered fashion to transfer data between said graphics processor and said memories, such that overall data transfer rate is faster than said memory cycle of one of said memories.

Claim 13

The apparatus of claim 10, wherein said graphics processor provides a write enable signal coupled to all of said memories for writing data into said memories.

Claim 14

The apparatus of claim 11, wherein said graphics processor provides a first row address on said address bus and all RAS signals strobing said first row address into said memories; said graphics processor then providing a first column address on said address bus; said graphics processor also providing data for each memory sequentially; and said graphics processor providing said CAS signals in said staggered fashion to coincide with presence of its corresponding data on said data bus, wherein data is written to said memories in said staggered fashion.

Claim 15

The apparatus of claim 11, wherein said graphics processor provides a separate row address on said address bus sequentially for each of said memories; said graphics processor providing said RAS signals in said staggered fashion to coincide with presence of its corresponding row address to strobe said separate row address into its corresponding memory in said staggered fashion; then, said graphics processor providing a first column address on said address bus and data on said data bus; said processor strobing all CAS signals to strobe in said first column address and data to said memories.

Claim 16

The apparatus of claim 11, wherein said graphics processor provides a separate output enable signal to each of said memories, wherein activation of each of said separate output enable signals in a staggered fashion causes data to be read from its corresponding memory, so that data can be read from said memories in a staggered fashion.

Claim 17

The apparatus of claim 14, wherein said graphics processor provides a first row address on said address bus and all RAS signals strobing said first row address into said memories; said graphics processor then providing a first column address on said address bus; said graphics processor also providing said CAS signals and said output enable signals in a staggered fashion, such that said first column address is strobed in and data read from said memories in said staggered fashion.

Claim 18

In a graphics display system having a host processor which provides instruction for providing an image to be displayed, an apparatus for providing pixel information for a raster scan display having pixels arranged in a plurality of horizontal lines to form said raster scan display, comprising: a plurality of memories arranged in an array accessed by row address data and column address data in a memory cycle; a graphics processor coupled to said memories; a first data bus coupled to said graphics processor; a data switcher coupled to said first data bus; a plurality of second data buses coupled to said data switcher, wherein each of said second data buses is coupled to its corresponding memory chips forming a column of said memory array; an address bus coupled to said graphics processor and said memories for coupling said row address data and said column address data from said graphics processor to said memories for accessing location in said memories; said graphics processor providing a separate row address strobe (RAS) signal and a separate column address strobe (CAS) signal to corresponding memories comprising a column of said array, said graphics processor coupling a read and a write enable signals to all chips of said memory, each of said RAS signals and each of said CAS signals being independently provided by said graphics processor and independently coupled to said memories; all of said RAS signals individually capable of having associated row address data which is unique from all other row address data associated with other RAS signals within said memory cycle and all of said CAS signals individually capable of having associated data which is unique from all other data associated with other CAS signals within said memory cycle; wherein staggering the strobing of either said RAS or CAS signals causes memories comprising said column of said array to be accessed in a staggered fashion to transfer data between said graphics processor and said memories, such that overall data transfer rate is faster than said memory cycle of one of said memories.

Claim 19

In a graphics display system having a host processor which provides instruction for providing an image to be displayed, an apparatus for providing pixel information for a raster scan display having pixels arranged in a plurality of horizontal lines to form said raster scan display, comprising: a plurality of memories arranged in an array accessed by row address data and column address data in a memory cycle; a graphics processor coupled to said memories; a first data bus coupled to said graphics processor; a data switcher coupled to said first data bus; a plurality of second data buses coupled to said data switcher, wherein each of said second data buses is coupled to its corresponding memory chips forming a column of said memory array; an address bus coupled to said graphics processor and said memories for coupling said row address data and said column address data from said graphics processor to said memories for accessing location in said memories; said graphics processor providing a separate row address strobe (RAS) signal and a separate column address strobe (CAS) signal to corresponding memories comprising a column of said array, said graphics processor coupling a read and a write enable signals to all chips of said memory, each of said RAS signals and each of said CAS signals being independently provided by said graphics processor and independently coupled to said memories; all of said RAS signals individually capable of having associated row address data which is unique from all other row address data associated with other RAS signals within said memory cycle and all of said CAS signals individually capable of having associated data which is unique from all other data associated with other CAS signals within said memory cycle; wherein staggering the strobing of either said RAS or CAS signals causes memories comprising said column of said array to be accessed in a staggered fashion to transfer data between said graphics processor and said memories, such that overall data transfer rate is faster than said memory cycle of one of said memories.

Claim 20

The apparatus of claim 16 further comprising: an address switcher coupled to said first address bus; a plurality of second address buses coupled to said address switcher, wherein instead of said first address bus being coupled to said memories, each of said second address buses being coupled to corresponding memories comprising a column of said array; said address switcher for providing address signals on said first bus onto one or all of said second address buses.

Claim 21

In an apparatus for providing video data for a raster scan display having pixels along a plurality of horizontal lines and where a graphics processor is coupled to a memory having a plurality of memory devices, said memory devices accessed by row and column address data within a memory cycle and where pixel data for said display is processed by said processor and stored in said memory, said processor manipulating said pixel data, an improvement comprising: a plurality of separate row address strobe (RAS) lines, one RAS line coupled to each of said memories for strobing in a row address signal; a plurality of separate column address strobe (CAS) lines, one CAS line coupled to each of said memories for strobing in a column address signal; each of said RAS lines and each of said CAS lines being independently provided by said graphics processor and independently coupled to said memory devices; all of said RAS lines individually capable of having associated row address data which is unique from all other row address data associated with other RAS lines within said memory cycle and all of said CAS lines individually capable of having associated data which is unique from all other data associated with other CAS lines within said memory cycle; wherein said RAS or CAS lines are strobed at staggered time intervals to provide data transfers between said memory and said graphics processor at a rate faster than said memory cycle time of one of said memories.

Claim 22

In an apparatus for providing video data for a raster scan display having pixels along a plurality of horizontal lines and where a graphics processor is coupled to a memory having a plurality of memory devices, said memory devices accessed by row and column address data within a memory cycle and where pixel data for said display is processed by said processor and stored in said memory, said processor manipulating said pixel data, an improvement comprising: a plurality of separate row address strobe (RAS) lines, one RAS line coupled to each of said memories for strobing in a row address signal; a plurality of separate column address strobe (CAS) lines, one CAS line coupled to each of said memories for strobing in a column address signal; each of said RAS lines and each of said CAS lines being independently provided by said graphics processor and independently coupled to said memory devices; all of said RAS lines individually capable of having associated row address data which is unique from all other row address data associated with other RAS lines within said memory cycle and all of said CAS lines individually capable of having associated data which is unique from all other data associated with other CAS lines within said memory cycle; wherein said RAS or CAS lines are strobed at staggered time intervals to provide data transfers between said memory and said graphics processor at a rate faster than said memory cycle time of one of said memories.