US5274646A
Expired / Lapsed
US
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Excessive error correction control
Assignee: International Business Machines Corp
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Filing: 1991-04-17
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Granted: 1993-12-28
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Expires: 2011-04-17
Abstract
Abstract A method of automatically invoking a recoverable and fault tolerant implementation of the complemented/recomplemented (C/R) error correction method without the assistance of a service processor when an excessive error is detected in main storage (MS) by ECC logic circuits. An excessive error is not correctable by the ECC. These novel changes to the C/R method increase its effectiveness and protect the C/R hardware against random failure. Further, if an excessive error is corrected in a page in MS, an excessive error reporting process is provided for controlling the reporting using a storage map to determine if a previous correction in that page has been reported. If it has been reported, then no further reporting of soft excessive errors is made for that page. A service processor is signaled in parallel to update its persistent copy of the storage map so that on a next initializations of MS the memory map can be restored in the memory. The memory map is used to assist the repair of failing parts of MS, and is reset after MS is repaired.
Inventors
- 👤 Thomas M. Brey
- 👤 Matthew A. Krygowski
- 👤 Bruce L. McGilvray
- 👤 Trinh H. Nguyen
- 👤 William W. Shen
- 👤 Arthur J. Sutton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 08:06
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0766; G06F11/0772; G06F11/0706; G06F11/073; G06F11/0793; G06F11/08; G06F11/10; G06F11/1008; G06F11/1048; G06F11/16; G06F11/1666; G06F11/167
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
227 words
A method for handling storage errors, the method comprising the steps of: fetch requesting by a processor of data from a memory in a data processing system, and responding by a memory controller with the data and indicating any excessive error in the data detected with ECC bits; refetch requesting by the processor of the data in response to receiving an excessive error indication from the memory controller, initiating a complement/recomplement (C/R) error correction method in response to the refetch request for the erroneous data using a first fetch, a first store, a second fetch and a second store of the data, including: buffering the data and ECC obtained by the first fetch and by the second fetch during the C/R method, and doing a double inversion on at least an erroneous portion of the data in attempting to correct the excessive error; sending the data to the requesting processor obtained by the second fetch in the C/R method and indicating if the data and ECC contain no error, any corrected hard and/or soft error(s), any corrected excessive hard or soft error(s), any corrected excessive hard or soft error(s), or non-correctable error(s); and pipelining fetch and refetch requests from one or more processors to the storage controller for prioritizing memory accesses for fetch requests and for operations of the C/R method for different data in the memory.
Claim 2
Independent Claim
227 words
A method for handling storage errors, the method comprising the steps of: fetch requesting by a processor of data from a memory in a data processing system, and responding by a memory controller with the data and indicating any excessive error in the data detected with ECC bits; refetch requesting by the processor of the data in response to receiving an excessive error indication from the memory controller, initiating a complement/recomplement (C/R) error correction method in response to the refetch request for the erroneous data using a first fetch, a first store, a second fetch and a second store of the data, including: buffering the data and ECC obtained by the first fetch and by the second fetch during the C/R method, and doing a double inversion on at least an erroneous portion of the data in attempting to correct the excessive error; sending the data to the requesting processor obtained by the second fetch in the C/R method and indicating if the data and ECC contain no error, any corrected hard and/or soft error(s), any corrected excessive hard or soft error(s), any corrected excessive hard or soft error(s), or non-correctable error(s); and pipelining fetch and refetch requests from one or more processors to the storage controller for prioritizing memory accesses for fetch requests and for operations of the C/R method for different data in the memory.
Claim 3
Dependent Claim
81 words
A method for handling storage errors as defined in claim 1, the buffering step further comprising: providing a data buffer and at least one status buffer, entries in the data buffer respectively receiving a plurality of data units of a data line addresses in the memory by a requesting processor, corresponding entries in the status buffer receiving a status indicator of whether or not an excessive error is detected in a data unit in a corresponding entry in the data buffer.
Claim 4
Dependent Claim
79 words
A method for handling storage errors as defined in claim 2, the C/R method further comprising the steps of: microcode-accessing a page map with fields representing page frames in the memory to test the state of a field for a page frame having a currently requested address of the data unit having the excessive error, and setting on the field if found in an off state to indicate an excessive error has been found in the respective page frame.
Claim 5
Dependent Claim
38 words
A method for handling storage errors as defined in claim 3, the C/R method further comprising the steps of: interrupting the requesting processor for executing a software operating system (OS) if the accesses field is found set off.
Claim 6
Dependent Claim
44 words
A method for handling storage errors as defined in claim 3, the C/R method further comprising the steps of: continuing execution of the requesting processor without interruption upon finding the accessed field is set on when the C/R method has corrected an excessive error.
Claim 7
Dependent Claim
45 words
A method for handling storage errors as defined in claim 3, the C/R method further comprising the step of: reporting an excessive error condition to a service processor of the system when an excessive error is first found in any page frame of the memory.
Claim 8
Dependent Claim
38 words
A method for handling storage errors as defined in claim 6, the C/R method further comprising the step of: notifying a service processor if any excessive hard error is found for the page frame containing the current request.
Claim 9
Dependent Claim
56 words
A method for handling storage errors as defined in claim 17, the C/R method further comprising the step of: updating by the service processor of a page map in persistent storage to conform to the page map maintained by microcode in volatile system memory for enabling the service processor to initialize the map in volatile memory.
Claim 10
Dependent Claim
45 words
A method for handling storage errors as defined in claim 15, the C/R method further comprising the step of: notifying OS of special error characters detected in an accessed data unit only if the respective field in the page map is in set off state.
Claim 11
Dependent Claim
94 words
A method for handling storage errors as defined in claim 2, the C/R method further comprising: buffering a data line comprising a plurality of data units and associated ECC (DU+ECC) in which any one or more of the DU+ECC has one or more erroneous bits in the first fetch and second fetch parts of the C/R method; and not inverting any DU+ECC not having an excessive error in any phase of the C/R method, but inverting in the first store and second fetch parts of the C/R method any DU+ECC having an excessive error.
Claim 12
Dependent Claim
78 words
A method for handling storage errors as defined in claim 10, enabling a retry of the C/R method in case of failure of hardware used by the C/R method, further comprising: re-inverting each erroneous DU+ECC being buffered in an inverted form by the buffering step if a hardware failure occurs, but not inverting any non-erroneous DU+ECC, and storing all DU+ECC in the in their original location in the data line to enable a retry of the C/R method.
Claim 13
Dependent Claim
99 words
A method for handling storage errors as defined in claim 2, the C/R method further comprising the steps of: inverting all bits in a data unit and its ECC for the first store and after the second fetch of the C/R method when the status information indicates an excessive error exists in the data unit and/or ECC; and sending the twice inverted data unit and ECC with status information to the requesting processor after the second fetch of the C/R method, the status information signalling if correction is obtained for the excessive error in the data unit and/or ECC.
Claim 14
Dependent Claim
50 words
A method for handling storage errors as defined in claim 12, the C/R method further comprising the steps of: continuing to execute the current program without interruption in the requesting processor when the C/R method corrects an excessive error in any one or more data units of the data line.
Claim 15
Dependent Claim
85 words
A method for handling storage errors as defined in claim 12, the C/R method further comprising the steps of: providing a plurality of status buffers for containing the same status indication for each data unit in a corresponding entry in the data buffer; comparing the content of the status buffers for a data unit being accessed in the data buffer; and signalling an error condition for the current operation of the C/R method when the comparing step finds unequal contents for the plural status buffers.
Claim 16
Dependent Claim
87 words
A method for handling storage errors as defined in claim 14, the C/R method further comprising the steps of: also providing a parity bit for each status indication in each entry of the status buffers; parity-checking the contents of the status buffers for a parity error when the status indication for a data unit is being accessed in all status buffers; and using one of the accessed status indications to control the C/R method only if the parity-checking step indicates no parity error for that status indication.
Claim 17
Dependent Claim
57 words
A method for handling storage errors as defined in claim 15, the C/R method further comprising the steps of: signalling an error condition for the current operation of the C/R method when the parity-checking step finds a parity error for all status indications in the status buffers being accessed for a data unit in the data buffer.
Claim 18
Dependent Claim
58 words
A method for handling storage errors as defined in claim 16, the C/R method further comprising the steps of: re-writing a default status indication indicating no excessive error with a correct parity indication if bad parity is indicated by the parity checking step for any of the status buffers to increase the fault tolerance of the C/R method.
Claim 19
Dependent Claim
66 words
A method for handling storage errors as defined in claim 16, the C/R method further comprising the steps of: monitoring the number of parity errors occuring in the status buffer contents; and generating an interruption to the requesting processor when the monitoring step finds the number of parity errors exceed a predetermined threshold number to indicate repair is needed to means for executing the C/R method.
Claim 20
Dependent Claim
117 words
A method for handling storage errors as defined in claim 14, the C/R method further comprising the steps of: inpointer addressing of corresponding entries in all of the plural status buffers for writing a status indication into all status buffers for the C/R method, and outpointer addressing of all corresponding entries in all status buffers for reading a status indication for a data unit being accessed in the data buffer for the C/R method; comparing the content of the accessed entries in all status buffer being inpointer addressed or outpointer addressed; and indicating an error condition for the current C/R method if the comparing step does not find an equal comparison of the compared status buffer contents.
Claim 21
Dependent Claim
46 words
A method for handling storage errors as defined in claim 19, the C/R method further comprising the steps of: generating a parity indication for each status indication and including the parity indication with the status indication in the content of each status buffer entry being written.
Claim 22
Dependent Claim
91 words
A method for handling storage errors as defined in claim 19, the C/R method further comprising the steps of: providing an inpointer register for containing the inpointer addressing for each buffer and an outpointer register for containing the outpointer addressing for each buffer; comparing the content of all outpointer registers required to access corresponding entries in the buffers; and indicating an error condition for the current C/R method if any comparing step does not find an equal comparison of the compared contents of the inpointer registers or of the outpointer registers.
Claim 23
Independent Claim
271 words
A method for handling storage errors, the method comprising the steps of: fetch requesting by a processor of data from a memory in a data processing system, and responding by a memory controller with the data and indicating any excessive error in the data detected with ECC bits; refetch requesting by the processor of the data in response to receiving an excessive error indication from the memory controller, initiating a complement/recomplement (C/R) error correction method in response to the refetch request for the erroneous data using a first fetch, a first store, a second fetch and a second store of the data, including: buffering the data and ECC obtained by the first fetch and by the second fetch during the C/R method, and doing a double inversion on at least an erroneous portion of the data in attempting to correct the excessive error; sending the data to the requesting processor obtained by the second fetch in the C/R method and indicating if the data and ECC contain no error, any corrected hard and/or soft error(s), any corrected excessive hard or soft error(s), or non-correctable error(s); detecting for a failure in the hardware performing the C/R method; indicating a part of the C/R method in which an erroneous data unit and its associated ECC bits are inverted by the C/R method; and re-inverting and storing an erroneous data unit and associated ECC bits in their original location in response to the detecting step detecting a hardware failure if the indicating step finds they are inverted to enable recovery of the data unit and ECC by enabling a retry of the C/R method.
Claim 24
Independent Claim
271 words
A method for handling storage errors, the method comprising the steps of: fetch requesting by a processor of data from a memory in a data processing system, and responding by a memory controller with the data and indicating any excessive error in the data detected with ECC bits; refetch requesting by the processor of the data in response to receiving an excessive error indication from the memory controller, initiating a complement/recomplement (C/R) error correction method in response to the refetch request for the erroneous data using a first fetch, a first store, a second fetch and a second store of the data, including: buffering the data and ECC obtained by the first fetch and by the second fetch during the C/R method, and doing a double inversion on at least an erroneous portion of the data in attempting to correct the excessive error; sending the data to the requesting processor obtained by the second fetch in the C/R method and indicating if the data and ECC contain no error, any corrected hard and/or soft error(s), any corrected excessive hard or soft error(s), or non-correctable error(s); detecting for a failure in the hardware performing the C/R method; indicating a part of the C/R method in which an erroneous data unit and its associated ECC bits are inverted by the C/R method; and re-inverting and storing an erroneous data unit and associated ECC bits in their original location in response to the detecting step detecting a hardware failure if the indicating step finds they are inverted to enable recovery of the data unit and ECC by enabling a retry of the C/R method.
Claim 25
Dependent Claim
39 words
A method for handling storage errors as defined in claim 22, indicating step in the C/R method further comprising: indicating when the phase of the C/R method is in the first store or second fetch of the C/R method.
Claim 26
Dependent Claim
257 words
A process for reporting excessive error conditions to a memory map having entries representing page frames in a storage unit in a data processing system, the map entries reporting excessive error conditions detected for respective page frames, comprising the steps of: fetching in the storage unit by a storage controller of a data unit requested by a processor, and detecting and correcting any errors in the data unit up to a maximum number of correctable errors determined by ECC bits with the data unit for providing a predetermined maximum ECC error-correction capability for each data unit; invoking in the storage controller complement/recomplement (C/R) error correction operations upon the detection of an excessive error, which comprises multiple errors exceeding the ECC error-correction capability; re-fetching the data unit to attempt C/R error correction to correct any hard error of the data unit and using the ECC bits to correct any soft error of the data unit; accessing by the requesting processor of the map, and detecting in the map an entry for a currently accessed page frame, and sensing in the entry for a report field indicating an excessive error condition was previously reported for the current page frame; and interrupting the requesting processor operation for communicating with the control program if the report field does not indicate any excessive error condition was previously reported, and then setting the entry to an excessive error reported state, but not interrupting operation by the requesting processor if the accessed entry indicates an excessive error was previously reported for the page frame.
Claim 27
Dependent Claim
257 words
A process for reporting excessive error conditions to a memory map having entries representing page frames in a storage unit in a data processing system, the map entries reporting excessive error conditions detected for respective page frames, comprising the steps of: fetching in the storage unit by a storage controller of a data unit requested by a processor, and detecting and correcting any errors in the data unit up to a maximum number of correctable errors determined by ECC bits with the data unit for providing a predetermined maximum ECC error-correction capability for each data unit; invoking in the storage controller complement/recomplement (C/R) error correction operations upon the detection of an excessive error, which comprises multiple errors exceeding the ECC error-correction capability; re-fetching the data unit to attempt C/R error correction to correct any hard error of the data unit and using the ECC bits to correct any soft error of the data unit; accessing by the requesting processor of the map, and detecting in the map an entry for a currently accessed page frame, and sensing in the entry for a report field indicating an excessive error condition was previously reported for the current page frame; and interrupting the requesting processor operation for communicating with the control program if the report field does not indicate any excessive error condition was previously reported, and then setting the entry to an excessive error reported state, but not interrupting operation by the requesting processor if the accessed entry indicates an excessive error was previously reported for the page frame.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-12-27 | 1997-06-28 | 1997-12-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-12-27 | 2001-06-28 | 2001-12-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-12-27 | 2005-06-28 | 2005-12-28 | $7700.00 | Window Closed / Lapsed |