US4604751A
Expired / Lapsed
US
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Error logging memory system for avoiding miscorrection of triple errors
Assignee: International Business Machines Corp
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Filing: 1984-06-29
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Granted: 1986-08-05
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Expires: 2004-06-29
Abstract
Abstract Miscorrection of triple errors is avoided in a memory system equipped with a single bit error detection and correction/double bit error detection code by providing a double bit error logging technique. The address of each fetched word is logged in which a double bit error is detected. The address of each fetched word in which a single bit error is detected is compared with all logged addresses. If a coincidence is found between the compared addresses, a triple bit error alerting signal is generated and error recovery procedures are initiated.
Inventors
- 👤 Frederick J. Aichelmann, Jr.
- 👤 Philip M. Ryan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 02:10
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1012; G06F11/1024
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
159 words
Means for producing a suspected triple bit error alerting signal, said signal producing means extending the error detection capability of a single bit error detection and correction/double bit error detection code means used in a memory system wherein multiple bit word signals are fetched from memory from respective memory addresses and applied to said code means, said signal producing means including means for storing first signals representing the addresses of blocks of fetched word signals wherein a double bit error is detected by said code means, address comparison means receiving said stored first signals, means for applying to said address comparison means second signals representing the address of each fetched word wherein a single bit error is detected by said code means, said address comparison means producing said suspected triple bit error alerting signal upon coincidence of the addresses of said double bit error words and said single bit error word represented by said first and second signals respectively.
Claim 2
Dependent Claim
159 words
Means for producing a suspected triple bit error alerting signal, said signal producing means extending the error detection capability of a single bit error detection and correction/double bit error detection code means used in a memory system wherein multiple bit word signals are fetched from memory from respective memory addresses and applied to said code means, said signal producing means including means for storing first signals representing the addresses of blocks of fetched word signals wherein a double bit error is detected by said code means, address comparison means receiving said stored first signals, means for applying to said address comparison means second signals representing the address of each fetched word wherein a single bit error is detected by said code means, said address comparison means producing said suspected triple bit error alerting signal upon coincidence of the addresses of said double bit error words and said single bit error word represented by said first and second signals respectively.
Claim 3
Dependent Claim
115 words
The apparatus defined in claim 1 and further comprising error recovery means responsive to said alerting signal, respective valid fetch syndrome signal and fetched word signal having a detected single bit error, said correction means correcting each said fetched word signal using said respective syndrome signal to produce a first corrected word signal, when said alerting signal is produced by said address comparison means, word storage means receiving each said first corrected word signal, complement/recomplement (C/RC) means receiving said single bit error word signal corresponding to said first corrected word signal and producing a recomplemented corrected word signal, and ECC logic means receiving each said recomplemented word signal and producing a respective C/RC syndrom signal.
Claim 4
Dependent Claim
29 words
The apparatus defined in claim 2 and further including means for evaluating said C/RC syndrome signal and producing a first output signal if said C/RC syndrome signal is zero.
Claim 5
Dependent Claim
29 words
The apparatus defined in claim 3 wherein said means for evaluating said C/RC syndrome signal produces a second output signal if said C/RC syndrome signal is even or odd/invalid.
Claim 6
Dependent Claim
27 words
The apparatus defined in claim 4 wherein said means for evaluating said C/RC syndrome signal produces a third output signal if said C/RC syndrome signal is valid.
Claim 7
Dependent Claim
84 words
The apparatus defined in claim 5 and further inclduing additional ECC logic means responsive to said third output signal, said recomplemented word signal and said C/RC syndrome signal said additional ECC logic means correcting said recomplemented word signal using said C/RC syndrome signal to produce a second corrected word signal, when said third output signal is produced, and comparison means receiving said second corrected word signal and said first corrected word signal and producing a fourth output signal upon equality of the compared signals.
Claim 8
Dependent Claim
45 words
The apparatus defined in claim 2 and further including exclusive ORing means receiving said single bit error word signal and said recomplemented word signal and producing a fifth output signal representing the number, if any, of stuck faults in said single bit error word signal.
Claim 9
Dependent Claim
61 words
The apparatus defined in claim 7 and further including means for counting the number of stuck fault representations in said fifth output signal and producing a sixth output signal when said number equals two, and means applying said sixth output signal to said means for storing the addresses of blocks of fetched word signals wherein a double bit error is detected.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-08-04 | 1990-02-03 | 1990-08-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-08-04 | 1994-02-03 | 1994-08-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-08-04 | 1998-02-03 | 1998-08-05 | $7700.00 | Window Closed / Lapsed |