Time-shared, multi-phase memory accessing system having automatically updatable error logging means

Claim 1

In combination: means providing items of digital data, each having an associated check code chosen to permit the indication of a plurality of different types of data error conditions which may be present with respect to said items of data; signal pattern generation means to which said items of data and their associated error check codes are sequentially applied, said signal pattern generating means being responsive to said data items and associated check codes to generate one of a plurality of different data error signal patterns indicating which if any of said plurality of different types of data error conditions is present with respect to each item of data; and error log circuitry to which the data error signal patterns generated by said signal pattern generation means are applied; said error log circuitry including first means for decoding said signal patterns and in response to said decoding providing indications of the occurrence of at least two of said different types of error conditions which may be present with respect to a plurality of data items applied to said signal pattern generation means over a predetermined time period; said error log circuitry also including second means responsive to said signal patterns and to said indications of different types of data error conditions provided by said first means for establishing priorities between particular applied data error signal patterns and for indicating the highest priority data error signal pattern obtained for a plurality of data error signal patterns applied to said error log circuitry over said predetermined time period.