Error correcting and controlling system

Claim 2

In an error correcting and controlling system in which an error check bit for correcting random t-bit errors (t≧2) and detecting (t+1)-bit errors is added to data, and in utilizing said data, t-bit errors are automatically corrected based on said data and said added error check bit and (t+1)-bit errors are similarly detected, said error correcting and controlling system comprises: syndrome generating means for generating syndrome outputs of said data, a memory for storing encoded error bit position information at address positions corresponding one-to-one to a portion only of the outputs of said syndrome generating means, addressing means responsive to said syndrome outputs of said syndrome generating means for addressing said memory to read out said bit position information corresponding to said syndrome outputs, and processing means for processing said syndrome outputs and said encoded error bit position information read out from said memory so as to decode the latter, to identify errors in said data, and to modify said data, whereby detection and correction of errors of said data are performed based on the stored contents of said memory.

Claim 3

In an error correcting and controlling system as set forth in claim 1, wherein said encoded error bit position information stored in said memory comprises a first portion indicating the identity, if any, of a first error, and a second portion indicating the identity, if any, of a second error, said system including first and second detecting means for detecting when said first and second portions, respectively, indicate absence of said first and second errors, respectively.

Claim 4

In an error correcting and controlling system as set forth in claim 1, wherein said encoded error bit position information stored in said memory comprises a first portion indicating the identity, if any, of a first error, and a second portion indicating the identity, if any, of a second error, said system including first and second decoding means for decoding the contents of said first and second portions, respectively, of said memory so as to provide an output identifying the presence, if any, of said first and second errors, respectively.

Claim 5

In an error correcting and controllng system in which an error check bit for correcting random t-bit errors (t≧2) and detecting (t+1)-bit errors is added to data, and in utilizing said data, t-bit errors are automatically corrected based on said data and said added error check bit and (t+1)-bit errors are similarly detected, said error correcting and controlling system comprises: syndrome generating means for generating syndrome outputs of said data, a memory for storing encoded error bit position information at address positions corresponding one-to-one to a portion only of the outputs of said syndrome generating means, addressing means responsive to said syndrome outputs of said syndrome generating means for addressing said memory to read out said bit position information corresponding to said syndrome outputs, and processing means for processing said syndrome outputs and said encoded error bit position information read out from said memory so as to decode the latter, to identify errors in said data, and to modify said data, whereby detection and correction of errors of said data are performed based on the stored contents of said memory; wherein encoded (t-1) error bit position information representative of error bit positions corresponding to the syndrome outputs of said syndrome generating means is stored in said memory, and said system further comprises encoded error bit position information generating means for generating the remaining one error bit position information based on said (t-1) error bit position information read from said memory and for carrying out the error bit correction by processing said encoded (t-1) error bit position information read out from said memory and said remaining one error bit position generated by said generating means.

Claim 6

In an error correcting and controllng system in which an error check bit for correcting random t-bit errors (t≧2) and detecting (t+1)-bit errors is added to data, and in utilizing said data, t-bit errors are automatically corrected based on said data and said added error check bit and (t+1)-bit errors are similarly detected, said error correcting and controlling system comprises: syndrome generating means for generating syndrome outputs of said data, a memory for storing encoded error bit position information at address positions corresponding one-to-one to a portion only of the outputs of said syndrome generating means, addressing means responsive to said syndrome outputs of said syndrome generating means for addressing said memory to read out said bit position information corresponding to said syndrome outputs, and processing means for processing said syndrome outputs and said encoded error bit position information read out from said memory so as to decode the latter, to identify errors in said data, and to modify said data, whereby detection and correction of errors of said data are performed based on the stored contents of said memory; wherein encoded (t-1) error bit position information representative of error bit positions corresponding to the syndrome outputs of said syndrome generating means is stored in said memory, and said system further comprises encoded error bit position information generating means for generating the remaining one error bit position information based on said (t-1) error bit position information read from said memory and for carrying out the error bit correction by processing said encoded (t-1) error bit position information read out from said memory and said remaining one error bit position generated by said generating means.

Claim 7

In an error correcting and controlling system as set forth in claim 4, wherein said encoded error bit information generating means comprises: a first register for holding said encoded (t-1) error bit position information read from said memory indicating a first error in this data, error bit position information extracting means for processing said encoded (t-1) error bit position information and said syndrome outputs from said syndrome generating means to develop information indicating a second error in said data, and a second register for holding said information indicating said second error in said data.

Claim 8

In an error correcting and controlling system as set forth in claim 5, wherein said system further comprises first and second decoding means connected to said first and second registers, respectively, for decoding said information indicating said first and second errors, respectively, and providing corresponding first and second decoder outputs for detection and correction of errors of said data.

Claim 9

In an error correcting and controlling system in which an error check bit for correcting random t-bit errors (t≧2) and detecting (t+1)-bit errors is added to data, and in utilizing said data, t-bit errors are automatically corrected based on said data and said added error check bit and (t+1)-bit errors are similarly detected, said error correcting and controlling system comprises: syndrome generating means for generating syndrome outputs of said data, a memory for storing encoded error bit position information at address positions corresponding one-to-one to a portion only of the outputs of said syndrome generating means, addressing means responsive to said syndrome outputs of said syndrome generating means for addressing said memory to read out said bit position information corresponding to said syndrome outputs, and processing means for processing said syndrome outputs and said encoded error bit position information read out from said memory so as to decode the latter, to identify errors in said data, and to modify said data, whereby detection and correction of errors of said data are performed based on the stored contents of said memory; wherein the system comprises a propriety check circuit connected to said syndrome generating means and said memory for checking whether or not a predetermined relationship exists between said error bit position information read from said memory and said syndrome produced by said syndrome generating means, whereby the error bit position information read from said memory is determined.

Claim 10

In an error correcting and controlling system in which an error check bit for correcting random t-bit errors (t≧2) and detecting (t+1)-bit errors is added to data, and in utilizing said data, t-bit errors are automatically corrected based on said data and said added error check bit and (t+1)-bit errors are similarly detected, said error correcting and controlling system comprises: syndrome generating means for generating syndrome outputs of said data, a memory for storing encoded error bit position information at address positions corresponding one-to-one to a portion only of the outputs of said syndrome generating means, addressing means responsive to said syndrome outputs of said syndrome generating means for addressing said memory to read out said bit position information corresponding to said syndrome outputs, and processing means for processing said syndrome outputs and said encoded error bit position information read out from said memory so as to decode the latter, to identify errors in said data, and to modify said data, whereby detection and correction of errors of said data are performed based on the stored contents of said memory; wherein the system comprises a propriety check circuit connected to said syndrome generating means and said memory for checking whether or not a predetermined relationship exists between said error bit position information read from said memory and said syndrome produced by said syndrome generating means, whereby the error bit position information read from said memory is determined.

Claim 11

An error correcting and controlling system for detecting random (t+1)-bit errors and correcting random t-bit errors in data supplied thereto, said system comprising: syndrome generating means responsive to said data for generating syndrome outputs in accordance with said data and with a syndrome inspection matrix characterizing said syndrome generating means; memory means for holding a plurality of encoded error bit position data, each encoded error bit position data corresponding to a respective one of said syndrome outputs, said memory means being addressably responsive to each respective one of said syndrome outputs for reading out said corresponding error bit position data; and processing means responsive to each respective one of said syndrome outputs and to said corresponding encoded error bit position data for processing same to detect said (t+1)-bit error in said data, and to correct said t-bit error in said data.

Claim 12

An error correcting and controlling system for detecting random (t+1)-bit errors and correcting random t-bit errors in data supplied thereto, said system comprising: syndrome generating means responsive to said data for generating syndrome outputs in accordance with said data and with a syndrome inspection matrix characterizing said syndrome generating means; memory means for holding a plurality of encoded error bit position data, each encoded error bit position data corresponding to a respective one of said syndrome outputs, said memory means being addressably responsive to each respective one of said syndrome outputs for reading out said corresponding error bit position data; and processing means responsive to each respective one of said syndrome outputs and to said corresponding encoded error bit position data for processing same to detect said (t+1)-bit error in said data, and to correct said t-bit error in said data.

Claim 13

An error correcting and controlling system as set forth in claim 8, wherein said encoded error bit position information stored in said memory comprises a first portion indicating the identity, if any, of a first error, and a second portion indicating the identity, if any, of a second error, said processing means including first and second detecting means for detecting when said first and second portions, respectively, indicate absence of said first and second errors, respectively.

Claim 14

An error correcting and controlling system as set forth in claim 8, wherein said encoded error bit position information stored in said memory comprises a first portion indicating the identity, if any, of a first error, and a second portion indicating the identity, if any, of a second error, said processing means including first and second decoding means for decoding the contents of said first and second portions, respectively, of said memory so as to provide an output identifying the presence, if any, of said first and second errors, respectively.

Claim 15

An error correcting and controlling system for detecting random (t+1)-bit errors and correcting random t-bit errors in data supplied thereto, said system comprising: syndrome generating means responsive to said data for generating syndrome outputs in accordance with said data and with a syndrome inspection matrix characterizing said syndrome generating means; memory means for holding a plurality of encoded error bit position data, each encoded error bit position data corresponding to a respective one of said syndrome outputs, said memory means being addressably responsive to each respective one of said syndrome outputs for reading out said corresponding error bit position data; and processing means responsive to each respective one of said syndrome outputs and to said corresponding encoded error bit position data for processing same to detect said (t+1)-bit error in said data, and to correct said t-bit error in said data; wherein said memory means stores all encoded error bit position information except for a remaining one of said error bit position information, said system including error bit position information generating means for generating the remaining one of said error bit position information from that encoded error bit position information read from said memory means so as to derive all of said encoded error bit position information for detection and correction of said data.

Claim 16

An error correcting and controlling system for detecting random (t+1)-bit errors and correcting random t-bit errors in data supplied thereto, said system comprising: syndrome generating means responsive to said data for generating syndrome outputs in accordance with said data and with a syndrome inspection matrix characterizing said syndrome generating means; memory means for holding a plurality of encoded error bit position data, each encoded error bit position data corresponding to a respective one of said syndrome outputs, said memory means being addressably responsive to each respective one of said syndrome outputs for reading out said corresponding error bit position data; and processing means responsive to each respective one of said syndrome outputs and to said corresponding encoded error bit position data for processing same to detect said (t+1)-bit error in said data, and to correct said t-bit error in said data; wherein said memory means stores all encoded error bit position information except for a remaining one of said error bit position information, said system including error bit position information generating means for generating the remaining one of said error bit position information from that encoded error bit position information read from said memory means so as to derive all of said encoded error bit position information for detection and correction of said data.

Claim 17

An error correcting and controlling system for detecting random (t+1)-bit errors and correcting random t-bit errors in data supplied thereto, said system comprising: syndrome generating means responsive to said data for generating syndrome outputs in accordance with said data and with a syndrome inspection matrix characterizing said syndrome generating means; memory means for holding a plurality of encoded error bit position data, each encoded error bit position data corresponding to a respective one of said syndrome outputs, said memory means geing addressably responsive to each respective one of said syndrome outputs for reading out said corresponding error bit position data; and processing means responsive to each respective one of said syndrome outputs and to said corresponding encoded error bit position data for processing same to detect said (t+1)-bit error in said data, and to correct said t-bit error in said data; said system including check circuit means connected to said syndrome generating means and to said memory means for checking whether or not a predetermined relationship exists between said encoded error bit position information read from said memory means and said syndrome produced by said syndrome generating means, whereby the encoded error bit position information read from said memory means is determined and any error bits are corrected.

Claim 18

An error correcting and controlling system for detecting random (t+1)-bit errors and correcting random t-bit errors in data supplied thereto, said system comprising: syndrome generating means responsive to said data for generating syndrome outputs in accordance with said data and with a syndrome inspection matrix characterizing said syndrome generating means; memory means for holding a plurality of encoded error bit position data, each encoded error bit position data corresponding to a respective one of said syndrome outputs, said memory means geing addressably responsive to each respective one of said syndrome outputs for reading out said corresponding error bit position data; and processing means responsive to each respective one of said syndrome outputs and to said corresponding encoded error bit position data for processing same to detect said (t+1)-bit error in said data, and to correct said t-bit error in said data; said system including check circuit means connected to said syndrome generating means and to said memory means for checking whether or not a predetermined relationship exists between said encoded error bit position information read from said memory means and said syndrome produced by said syndrome generating means, whereby the encoded error bit position information read from said memory means is determined and any error bits are corrected.