US5479630A
Expired / Lapsed
US
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Hybrid cache having physical-cache and virtual-cache characteristics and method for accessing same
Assignee: ARM Finance Overseas Ltd
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Filing: 1994-03-11
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Granted: 1995-12-26
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Expires: 2014-03-11
Abstract
Abstract A cache memory system includes a primary cache characterized by a virtual index and physical tags, and a secondary cache characterized by a physical index and physical tag. Thus, the cache system forms a hybrid of physical-cache and virtual-cache characteristics. Further, the secondary cache includes a primary index segment for each line of secondary cache. The primary index segment corresponds to a portion of the virtual address for the contents stored at the respective secondary-cache line. Further, primary cache is maintained as a subset of secondary cache. To maintain the primary cache in such a way, the primary index segment is used to generate an index into primary cache to identify each potential primary-cache block which may be a subset of a secondary-cache block to be changed. When a secondary-cache block is to be invalidated, flushed or overwritten, the corresponding primary-cache blocks are identified and invalidated. The primary index segment also serves as a virtual tag for assuring that at any given time primary cache stores no more than one valid block corresponding to the same physical locations. When a secondary-cache hit occurs in response to a secondary-cache physical tag check, the primary index segment is compared to a portion of the virtual address. If the segment does not match, then primary cache may already have a word stored which corresponds to the desired physical location. As a result, the corresponding block in primary cache is invalidated and the primary index segment in secondary cache is changed to the current virtual address segment.
Inventors
- 👤 Earl A. Killian
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 18:26
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0893; G06F12/0897; G06F12/10; G06F12/1027; G06F12/1045; G06F12/1054; G06F12/0844; G06F12/0846; G06F12/0848
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
284 words
A method, in a computing device having a processor, a main memory and a cache memory system having a primary cache and a secondary cache, said method for accessing said primary cache using an n-bit virtual address having a virtual page number and a page offset, comprising the steps of: accessing an indexed primary-cache line using a virtual index, said primary cache line storing at least a first word, said virtual index being a first subset of the n bits forming said virtual address, said indexed primary-cache line storing a primary-cache physical tag; translating said n-bit virtual address into a translated address, including a translated m-bit physical address; comparing said primary-cache physical tag with a primary tag reference, said primary tag reference being a first subset of the m-bits forming said translated m-bit physical address; accessing a secondary-cache line with a physical index in response to a mismatch between said primary-cache physical tag and said primary tag reference, said physical index being a second subset of the m bits forming said translated physical address, said secondary-cache line comprising a secondary-cache physical tag, a second word and a primary index segment; checking said secondary-cache physical tag with a secondary tag reference to confirm a desired physical address is being accessed, said secondary tag reference being a third subset of the m-bits forming said translated physical address; and comparing said primary index segment to a primary index segment reference in response to a match between said secondary-cache physical tag and said secondary tag reference so to determine whether said second word is also addressed by said n-bit virtual address, said primary index segment reference being a second subset of the n bits forming said virtual address.
Claim 2
Independent Claim
284 words
A method, in a computing device having a processor, a main memory and a cache memory system having a primary cache and a secondary cache, said method for accessing said primary cache using an n-bit virtual address having a virtual page number and a page offset, comprising the steps of: accessing an indexed primary-cache line using a virtual index, said primary cache line storing at least a first word, said virtual index being a first subset of the n bits forming said virtual address, said indexed primary-cache line storing a primary-cache physical tag; translating said n-bit virtual address into a translated address, including a translated m-bit physical address; comparing said primary-cache physical tag with a primary tag reference, said primary tag reference being a first subset of the m-bits forming said translated m-bit physical address; accessing a secondary-cache line with a physical index in response to a mismatch between said primary-cache physical tag and said primary tag reference, said physical index being a second subset of the m bits forming said translated physical address, said secondary-cache line comprising a secondary-cache physical tag, a second word and a primary index segment; checking said secondary-cache physical tag with a secondary tag reference to confirm a desired physical address is being accessed, said secondary tag reference being a third subset of the m-bits forming said translated physical address; and comparing said primary index segment to a primary index segment reference in response to a match between said secondary-cache physical tag and said secondary tag reference so to determine whether said second word is also addressed by said n-bit virtual address, said primary index segment reference being a second subset of the n bits forming said virtual address.
Claim 3
Dependent Claim
57 words
The method of claim 1, in which said secondary-cache line further comprises a secondary-cache block, and further comprising the step of loading said primary-cache line with a block of words in response to a match between said primary index segment and said primary index segment reference, said block of words being a subset of said secondary-cache block.
Claim 4
Dependent Claim
54 words
The method of claim 1, further comprising the steps of writing back said indexed primary-cache line to said secondary cache line and changing said primary index segment at said secondary-cache line to equal said primary index segment reference in response to a mismatch between said primary index segment and said primary index segment reference.
Claim 5
Dependent Claim
98 words
The method of claim 1, in which said primary cache comprises a plurality of primary-cache lines, each one primary-cache line having a primary-cache block of j words and a primary-cache physical tag, and in which said secondary-cache comprises a plurality of secondary-cache lines, each one secondary-cache line having a secondary-cache block of k words and a secondary-cache physical tag and a primary index segment, and further comprising the step of invalidating each one primary-cache line which includes a primary-cache block which is a subset of a secondary-cache block identified for being any one of invalidated, flushed or overwritten.
Claim 6
Dependent Claim
38 words
The method of claim 1, further comprising the step of loading said secondary-cache line with a block of words from said main memory in response to a mismatch between said secondary-cache physical tag and said secondary tag reference.
Claim 7
Dependent Claim
85 words
The method of claim 5, further comprising the steps of: generating a new virtual index from said primary index segment; accessing primary cache at a plurality of primary-cache lines based upon the generated new virtual index, each one line of said plurality of primary-cache lines having a primary-cache physical tag; for each said one line, comparing said primary-cache physical tag with said primary tag reference; and invalidating said one line in response to a match between said primary-cache physical tag and said primary tag reference.
Claim 8
Dependent Claim
31 words
The method of claim 5, further comprising the steps of: generating a new virtual index from said primary index segment; and accessing a primary-cache line based upon said new virtual index.
Claim 9
Dependent Claim
45 words
The method of claim 7, wherein said step of generating a new virtual index comprises the step of: combining said primary index segment with a physical page offset, said physical page offset being a fourth subset of the m bits forming said translated physical address.
Claim 10
Dependent Claim
44 words
The method of claim 7, wherein said step of generating a new virtual index comprises the step of: combining said primary index segment with a virtual page offset, said virtual page offset being a third subset of the n bits forming said virtual address.
Claim 11
Dependent Claim
330 words
A cache memory system in a computing device having a processor, for responding to an n-bit virtual address having at least a virtual page number and a page offset, the system comprising: a primary cache for storing words, said primary cache organized into a plurality of primary-cache lines, each primary-cache line for storing a primary-cache physical tag and a block of said words, wherein j words form a primary-cache block, each primary cache line being accessible in response to a virtual index, wherein said virtual index is a first subset of said n bit virtual address; means for translating said n-bit virtual address to an m-bit physical address; a secondary cache for storing words, said secondary cache organized into a plurality of secondary-cache lines, each secondary-cache line for storing a secondary-cache physical tag for identifying a physical address, a primary index segment for identifying a virtual address, and a block of said words, wherein k words form a secondary-cache block each secondary cache line being accessible in response to a physical index wherein said physical index is a first subset of said m-bit physical address; means coupled to said primary cache for comparing a first select primary-cache physical tag stored in said primary cache with a primary-cache tag reference, wherein said primary-cache tag reference is a second subset of said m-bit physical address; means coupled to said secondary cache for comparing a select secondary-cache physical tag stored in said secondary cache with a secondary-cache tag reference wherein said secondary-cache tag reference is a third subset of said m-bit physical address; and means for comparing a select primary index segment stored in said secondary cache and a primary index segment reference in response to a match between said select secondary-cache physical tag and said secondary-cache tag reference so to determine whether a word in said secondary cache is the word addressed by said n-bit virtual address wherein said primary index segment reference is a second subset of said n-bit virtual address.
Claim 12
Dependent Claim
330 words
A cache memory system in a computing device having a processor, for responding to an n-bit virtual address having at least a virtual page number and a page offset, the system comprising: a primary cache for storing words, said primary cache organized into a plurality of primary-cache lines, each primary-cache line for storing a primary-cache physical tag and a block of said words, wherein j words form a primary-cache block, each primary cache line being accessible in response to a virtual index, wherein said virtual index is a first subset of said n bit virtual address; means for translating said n-bit virtual address to an m-bit physical address; a secondary cache for storing words, said secondary cache organized into a plurality of secondary-cache lines, each secondary-cache line for storing a secondary-cache physical tag for identifying a physical address, a primary index segment for identifying a virtual address, and a block of said words, wherein k words form a secondary-cache block each secondary cache line being accessible in response to a physical index wherein said physical index is a first subset of said m-bit physical address; means coupled to said primary cache for comparing a first select primary-cache physical tag stored in said primary cache with a primary-cache tag reference, wherein said primary-cache tag reference is a second subset of said m-bit physical address; means coupled to said secondary cache for comparing a select secondary-cache physical tag stored in said secondary cache with a secondary-cache tag reference wherein said secondary-cache tag reference is a third subset of said m-bit physical address; and means for comparing a select primary index segment stored in said secondary cache and a primary index segment reference in response to a match between said select secondary-cache physical tag and said secondary-cache tag reference so to determine whether a word in said secondary cache is the word addressed by said n-bit virtual address wherein said primary index segment reference is a second subset of said n-bit virtual address.
Claim 13
Dependent Claim
19 words
The cache system of claim 10 in which each one primary-cache block is a subset of a secondary-cache block.
Claim 14
Dependent Claim
38 words
The cache system of claim 10, further comprising means for invalidating a primary-cache line which includes a select primary-cache block which is a subset of a secondary-cache block identified for being any one of invalidated, flushed or overwritten.
Claim 15
Dependent Claim
82 words
The cache system of claim 10, further comprising: means for comparing said primary-cache tag reference to a second select primary-cache physical tag of a select primary-cache line accessed using a new virtual index wherein said new virtual index comprises said select primary index segment and a third subset of said n-bit virtual address; and means for invalidating said select primary-cache line accessed using said new virtual index in response to a match between said primary-cache physical tag and said primary-cache tag reference.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-12-25 | 1999-06-26 | 1999-12-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-12-25 | 2003-06-26 | 2003-12-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-12-25 | 2007-06-26 | 2007-12-26 | $7700.00 | Window Closed / Lapsed |