EP0206050A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Virtually addressed cache memory with physical tags
Assignee: HP Inc
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Filing: 1986-06-06
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Granted: —
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Expires: 2006-06-06
Abstract
Abstract A cache memory (21) is accessed in parallel with a translation lookaside buffer (23). The cache memory (21) is accessed with an index including bits from the virtual part as well as from the physical part of the virtual address (43) presented by a processor, and returns a physical tag (49) and a block of data (51). The physical tag (49) is compared with the physical page number (47) returned by the lookaside buffer (23), while the virtual tag (45) returned by the lookaside buffer (23) is compared to the virtual part of the presented virtual address (43). If both are matches, the data returned by the cache memory (21) is the data from the presented address and can be sent to the processor.
Inventors
- 👤 William R. Bryg
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 03:42
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027; G06F12/1045; G06F12/1054
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
258 words
A method'of retrieving data from a cache memory in a computer system comprising a processor, a translation lookaside buffer, a main memory and a cache memory, and using virtual memory addresses, characterized by the steps of: presenting a virtual address from the processor, said virtual address comprising a virtual part and a physical part; accessing the cache memory with an index comprising at least one but fewer than all of the bits from the virtual part of the virtual address and a plurality of bits from the physical part of the virtual address, to provide an output from the cache including a physical tag and a block of data; accessing the translation lookaside buffer in parallel with accessing the cache memory, using a plurality of bits from the virtual part of the virtual address, to provide an output from the translation lookaside buffer including a virtual tag and a physical page number; comparing the virtual tag with the virtual part of the virtual address and providing a first signal of the virtual tag matches the virtual part; comparing the physical tag with the physical page number from the translation lookaside buffer, and providing a second signal if the physical tag matches the physical page number; making available to the processor at least a portion of the block of data output from the cache; and providing a signal to the processor indicating that the data made available is the data from the virtual address presented by the processor if both the first signal and the second signal are present.
Claim 2
Independent Claim
258 words
A method'of retrieving data from a cache memory in a computer system comprising a processor, a translation lookaside buffer, a main memory and a cache memory, and using virtual memory addresses, characterized by the steps of: presenting a virtual address from the processor, said virtual address comprising a virtual part and a physical part; accessing the cache memory with an index comprising at least one but fewer than all of the bits from the virtual part of the virtual address and a plurality of bits from the physical part of the virtual address, to provide an output from the cache including a physical tag and a block of data; accessing the translation lookaside buffer in parallel with accessing the cache memory, using a plurality of bits from the virtual part of the virtual address, to provide an output from the translation lookaside buffer including a virtual tag and a physical page number; comparing the virtual tag with the virtual part of the virtual address and providing a first signal of the virtual tag matches the virtual part; comparing the physical tag with the physical page number from the translation lookaside buffer, and providing a second signal if the physical tag matches the physical page number; making available to the processor at least a portion of the block of data output from the cache; and providing a signal to the processor indicating that the data made available is the data from the virtual address presented by the processor if both the first signal and the second signal are present.
Claim 3
Dependent Claim
375 words
A hierarchical memory system for a computer using virtual memory addresses characterized by processor means (19) for presenting a virtual address, said virtual address comprising a virtual part and a physical part; memory means (13) for storing data at physical addresses; a cache memory (21;61,63) connected between the processor (19) and the memory (13), for storing selected blocks of data from the memory (13), capable of being accessed in response to a virtual address (43) presented by the processor (19) using an index comprising at least one but fewer than all of the bits from the virtual part of the virtual address (43) and a plurality of bits from the physical part of the virtual address (43), to provide an output from the cache memory (21;61,63) including a physical tag (64) and a block of data (68); a translation lookaside buffer (23;60) connected between the processor (19) and the memory (13) in parallel with the cache memory (21;61,63), for storing selected pairs of virtual addresses and corresponding physical addresses, capable of being accessed in parallel with access to the cache memory (21;61,63) using a plurality of bits from the virtual part of the virtual address (43), to provide an output from the translation lookaside buffer (23;60) including a virtual tag and a physical page number; a first comparator (53;62) responsive to the virtual tag from the translation lookaside buffer (23;60) and to the virtual part of the virtual address (43) presented by the processor (19) to provide a first signal if the virtual tag matches the virtual part of the virtual address (43); a second comparator (55;65) responsive to the physical. tag (64) from the cache memory (21;61,63) and to the physical page number from the translation lookaside buffer (23;60) to provide a second signal if the physical tag matches the physical page number; means (69,71) for making available to the processor at least a portion of the block of data (68) output from the cache memory (61,63); and means (57;75) responsive to the first and second signals for providing a third signal to the processor indicating that the data made available is the data from the virtual address presented by the processor (19) if both the first signal and the second signal are present.
Claim 4
Dependent Claim
375 words
A hierarchical memory system for a computer using virtual memory addresses characterized by processor means (19) for presenting a virtual address, said virtual address comprising a virtual part and a physical part; memory means (13) for storing data at physical addresses; a cache memory (21;61,63) connected between the processor (19) and the memory (13), for storing selected blocks of data from the memory (13), capable of being accessed in response to a virtual address (43) presented by the processor (19) using an index comprising at least one but fewer than all of the bits from the virtual part of the virtual address (43) and a plurality of bits from the physical part of the virtual address (43), to provide an output from the cache memory (21;61,63) including a physical tag (64) and a block of data (68); a translation lookaside buffer (23;60) connected between the processor (19) and the memory (13) in parallel with the cache memory (21;61,63), for storing selected pairs of virtual addresses and corresponding physical addresses, capable of being accessed in parallel with access to the cache memory (21;61,63) using a plurality of bits from the virtual part of the virtual address (43), to provide an output from the translation lookaside buffer (23;60) including a virtual tag and a physical page number; a first comparator (53;62) responsive to the virtual tag from the translation lookaside buffer (23;60) and to the virtual part of the virtual address (43) presented by the processor (19) to provide a first signal if the virtual tag matches the virtual part of the virtual address (43); a second comparator (55;65) responsive to the physical. tag (64) from the cache memory (21;61,63) and to the physical page number from the translation lookaside buffer (23;60) to provide a second signal if the physical tag matches the physical page number; means (69,71) for making available to the processor at least a portion of the block of data (68) output from the cache memory (61,63); and means (57;75) responsive to the first and second signals for providing a third signal to the processor indicating that the data made available is the data from the virtual address presented by the processor (19) if both the first signal and the second signal are present.
References Cited (Backward Citations)
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