Abstract A cache memory system in a data processor that has a main memory and a processing unit, the cache memory system including a virtually addressed storage cache. This virtually addressed storage cache is connected to the main memory for storing in storage cache locations preselected portions of data from the main memory. Each cache location includes a valid indicator to indicate the data in the cache location is current. A translation buffers is coupled to the storage cache, and translates a virtual address to a physical address. The backmap is coupled to the storage cache and the translation buffer, and invalidates data in the storage cache by generating an invalidate index to the cache location at which a valid indicator is to be cleared only when data in the storage cache is to be invalidated. The cache memory system includes at least one lockout register for storing addresses for data which may exist in more than one storage location. The backmap invalidates all copies of the data in the storage cache after every reference to data in the storage cache using an address in the lockout register.
A cache memory system in a data processor including a main memory and a processing unit, said cache memory system comprising: a virtually addressed storage cache connected to said main memory for storing in storage cache locations preselected portions of data from main memory, each said cache location including a valid indicator to indicate the data in said cache location is current; a translation buffer coupled to said storage cache, for translating a virtual address to a physical address; a backmap coupled to said storage cache and said translation buffer, for invalidating data in said storage cache by generating an invalidate index to the cache location at which a valid indicator is to be cleared only when data in the storage cache is to be invalidated; and further comprising at least one lockout register for storing addresses for data which may exist in more than one storage cache location, wherein said backmap invalidates all copies of the data in said storage cache after every reference to data in said storage cache using an address in a lockout register.
Claim 2
Dependent Claim
178 words
A cache memory system in a data processor including a main memory and a processing unit, said cache memory system comprising: a virtually addressed storage cache connected to said main memory for storing in storage cache locations preselected portions of data from main memory, each said cache location including a valid indicator to indicate the data in said cache location is current; a translation buffer coupled to said storage cache, for translating a virtual address to a physical address; a backmap coupled to said storage cache and said translation buffer, for invalidating data in said storage cache by generating an invalidate index to the cache location at which a valid indicator is to be cleared only when data in the storage cache is to be invalidated; and further comprising at least one lockout register for storing addresses for data which may exist in more than one storage cache location, wherein said backmap invalidates all copies of the data in said storage cache after every reference to data in said storage cache using an address in a lockout register.
Claim 3
Dependent Claim
21 words
The apparatus of claim 1, wherein said lockout register includes means for comparing read and write requests with said stored addresses.
Claim 4
Dependent Claim
24 words
The apparatus of claim 1, wherein said lockout register includes means for merging subsequent requests to a same data block as a first request.
Claim 5
Dependent Claim
42 words
The apparatus of claim 1, wherein said lockout register includes a completed lockout check bit for indicating when synonym checking for a miss is completed, and means for locking and unlocking said lockout register in dependence on said completed lockout check bit.