Patent US5479374A successfully refreshed from Google Patents.
US5479374A
Expired / Lapsed
US
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Semiconductor memory device employing sense amplifier control circuit and word line control circuit
Assignee: Toshiba Corp
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Filing: 1994-07-25
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Granted: 1995-12-26
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Expires: 2014-07-25
Abstract
Abstract A semiconductor memory device capable of reducing power consumption has a memory cell array, a plurality of address lines, a pair of data lines, an address transition detector circuit for outputting an address transition signal in response to a change in a signal on the address line, a sense amplifier, a sense amplifier control circuit for activating the sense amplifier in response to the address transition signal and deactivating the sense amplifier in response to the sense amplifier output signal, and a word line control circuit which deactivates the word lines within the memory cell array in response to the sense amplifier control circuit.
Inventors
- 👤 Tsuguo Kobayashi
- 👤 Tsukasa Shirotori
- 👤 Kazutaka Nogami
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 07:53
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22; G11C8/00; G11C8/18
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
252 words
A semiconductor memory device comprising: a memory cell array having a plurality of word lines for accessing data stored within the memory cell array; a plurality of address lines coupled to the memory cell array so as to designate a memory cell within the memory cell array; a pair of data lines coupled to the memory cell within the memory cell array for acquiring complementary data from the memory cell; an address transition detector circuit coupled to the address lines to output an address transition signal in response to a change in a signal on the address lines; an equalizer circuit coupled to the pair of data lines and responsive to the address transition signal to establish a signal having the same predetermined value on each of the pair of data lines; a sense amplifier coupled to the pair of data lines for generating a sense amplifier output signal in response to a change in potential on the pair of the data lines; a sense amplifier control circuit coupled to the address transition detector circuit and coupled to the sense amplifier, the sense amplifier control circuit activating the sense amplifier in response to the address transition signal and deactivating the sense amplifier in response to the sense amplifier output signal; and a word line control circuit coupled to the sense amplifier control circuit and to the memory cell array, wherein the word line control circuit deactivates the word lines within the memory cell array in response to the sense amplifier control circuit.
Claim 2
Dependent Claim
252 words
A semiconductor memory device comprising: a memory cell array having a plurality of word lines for accessing data stored within the memory cell array; a plurality of address lines coupled to the memory cell array so as to designate a memory cell within the memory cell array; a pair of data lines coupled to the memory cell within the memory cell array for acquiring complementary data from the memory cell; an address transition detector circuit coupled to the address lines to output an address transition signal in response to a change in a signal on the address lines; an equalizer circuit coupled to the pair of data lines and responsive to the address transition signal to establish a signal having the same predetermined value on each of the pair of data lines; a sense amplifier coupled to the pair of data lines for generating a sense amplifier output signal in response to a change in potential on the pair of the data lines; a sense amplifier control circuit coupled to the address transition detector circuit and coupled to the sense amplifier, the sense amplifier control circuit activating the sense amplifier in response to the address transition signal and deactivating the sense amplifier in response to the sense amplifier output signal; and a word line control circuit coupled to the sense amplifier control circuit and to the memory cell array, wherein the word line control circuit deactivates the word lines within the memory cell array in response to the sense amplifier control circuit.
Claim 3
Dependent Claim
49 words
The semiconductor memory device of claim 1 further comprising a decoder coupled to the address lines and to the word line control circuit, wherein the word line control circuit causes the decoder to disable the word lines in response to a signal generated by the sense amplifier control circuit.
Claim 4
Dependent Claim
77 words
The semiconductor memory device of claim 1 wherein the sense amplifier output signal comprises a pair of digital signals and wherein one of the digital signals becomes the logical complement of the other of the digital signals when data are present on the pair of data lines when the sense amplifier is activated and wherein the one of the digital signals becomes the same as the other of the digital signals when the sense amplifier is deactivated.
Claim 5
Dependent Claim
34 words
The semiconductor memory device of claim 3 wherein the sense amplifier control circuit deactivates the sense amplifier in response to one of the digital signals becoming different from the other of the digital signals.
Claim 6
Dependent Claim
60 words
The semiconductor memory device of claim 1 wherein the sense amplifier control circuit generates a sense amplifier control signal in response to the address transition signal and the sense amplifier output signal, wherein one value of the sense amplifier control signal activates the sense amplifier and wherein a second value of the sense amplifier control signal deactivates the sense amplifier.
Claim 7
Dependent Claim
33 words
The semiconductor memory device of claim 5 wherein the second value of the sense amplifier control signal causes the word line control circuit to deactivate the word lines in the memory cell array.
Claim 8
Dependent Claim
235 words
A semiconductor memory device comprising: a memory cell array having a plurality of word lines for accessing data stored within the memory cell array; a plurality of address lines coupled to the memory cell array so as to designate a memory cell within the memory cell array; a pair of data lines coupled to the memory cell within the memory cell array for acquiring complementary data from the memory cell; an address transition detector circuit coupled to the address lines to output an address transition signal in response to a change in a signal on the address lines; a sense amplifier coupled to the pair of data lines for generating a sense amplifier output signal in response to a change in potential on the pair of the data lines; a sense amplifier control circuit coupled to the address transition detector circuit and coupled to the sense amplifier to provide a control signal to the sense amplifier and to receive the sense amplifier output signal, the sense amplifier control circuit activating the sense amplifier in response to the address transition signal and deactivating the sense amplifier in response to the sense amplifier output signal; and a word line control circuit coupled to the sense amplifier control circuit and to the memory cell array, wherein the word line control circuit deactivates the word lines within the memory cell array in response to the sense amplifier control circuit.
Claim 9
Dependent Claim
235 words
A semiconductor memory device comprising: a memory cell array having a plurality of word lines for accessing data stored within the memory cell array; a plurality of address lines coupled to the memory cell array so as to designate a memory cell within the memory cell array; a pair of data lines coupled to the memory cell within the memory cell array for acquiring complementary data from the memory cell; an address transition detector circuit coupled to the address lines to output an address transition signal in response to a change in a signal on the address lines; a sense amplifier coupled to the pair of data lines for generating a sense amplifier output signal in response to a change in potential on the pair of the data lines; a sense amplifier control circuit coupled to the address transition detector circuit and coupled to the sense amplifier to provide a control signal to the sense amplifier and to receive the sense amplifier output signal, the sense amplifier control circuit activating the sense amplifier in response to the address transition signal and deactivating the sense amplifier in response to the sense amplifier output signal; and a word line control circuit coupled to the sense amplifier control circuit and to the memory cell array, wherein the word line control circuit deactivates the word lines within the memory cell array in response to the sense amplifier control circuit.
References Cited (Backward Citations)
US4947379A
Cited
US4922461A
Cited
US5228003A
Cited
US5025422A
Cited
US5193076A
Cited
US5214610A
Cited
US4972374A
Cited
US5343432A
Cited
US5327394A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-12-25 | 1999-06-26 | 1999-12-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-12-25 | 2003-06-26 | 2003-12-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-12-25 | 2007-06-26 | 2007-12-26 | $7700.00 | Window Closed / Lapsed |