Semiconductor memory

Claim 2

A semiconductor memory actuatable in response to a chip selection signal and address signals, comprising: a memory cell array having data lines; a selection signal generating circuit connected for generating an inner selection signal in response to the chip selection signal, the inner selection signal having an associated chip selecting state; a control signal generating circuit connected for detecting changes in the address signals and generating a first control signal in response to the change of each address signal used for the detection; and a signal changing circuit connected for deriving from said first control signal a second control signal for controlling said data lines of said memory cell array, a termination of the second control signal corresponding to a termination of said first control signal, wherein said signal changing circuit comprises means for delaying the termination of said second control signal relative to the termination of said first control signal when the inner selection signal is in the chip-selecting state.

Claim 3

A semiconductor memory as claimed in claim 1 wherein said signal changing circuit is operative to terminate said second control signal substantially simultaneously with the termination of said first control signal when inner selection signal is not in the chip-selecting state.

Claim 4

A semiconductor memory as claimed in claim 1 further comprising a data amplifier connected to said data lines and an output circuit connected to said data amplifier, and wherein said signal changing circuit is connected to said memory cell array, said amplifier and said output circuit such that said second control signal acts to precharge or equalize said data lines and to inhibit operation of said amplifier and said output circuit.

Claim 5

A semiconductor memory as claimed in claim 1 wherein said signal changing circuit comprises: first logical gate means connected for imparting a time delay to said first control signal when said inner selection signal is in the chip-selecting state; and second logical gate means connected to receive the delayed signal provided by said first logical gate means and the first control signal for effecting a logical disjunctive linkage of the delayed signal and the corresponding undelayed first control signal to thereby provide said second control signal.

Claim 6

A semiconductor memory as claimed in claim 1 wherein said memory cell array further has a first group of lines constituting word lines and a second group of lines constituting column select lines, and further comprising a selection line control circuit for generating a selection line control signal for deactivating at least one of said groups of lines of said memory cell array, said selection line control circuit comprising third logical gate means for deriving said selection line control signal from said first control signal when said inner selection signal is in the chip-selecting state.

Claim 7

A semiconductor memory as claimed in claim 5 further comprising a data amplifier, and wherein said memory cell array comprises a plurality of memory cells, a plurality of first transistors each having a control input connected to a respective word line and being disposed for connecting a respective memory cell to a respective data line, and a plurality of second transistors each having a control input connected to a respective column select line and being disposed for connecting a respective data line to said data amplifier.

Claim 8

A semiconductor memory comprising: a memory cell array; input terminals for receiving a chip selection signal and address signals; a selection signal generating circuit connected for generating an inner selection signal in response to the chip selection signal; a control signal generating circuit connected for detecting changes in the address signals and generating a first control signal in response to the change of each address signal used for the detection; and a signal width changing circuit connected for deriving from said first control signal a second control signal for controlling the operation of said memory cell array, wherein said signal width changing circuit comprises: first logical gate means connected for imparting a time delay to said first control signal when said inner selection signal is in the chip-selecting state; and second logical gate means connected to receive the delayed signal provided by said first logical gate means and the first control signal for effecting a logical disjunctive linkage of the delayed signal and the corresponding undelayed first control signal to thereby provide said second control signal.

Claim 9

A semiconductor memory comprising: a memory cell array; input terminals for receiving a chip selection signal and address signals; a selection signal generating circuit connected for generating an inner selection signal in response to the chip selection signal; a control signal generating circuit connected for detecting changes in the address signals and generating a first control signal in response to the change of each address signal used for the detection; and a signal width changing circuit connected for deriving from said first control signal a second control signal for controlling the operation of said memory cell array, wherein said signal width changing circuit comprises: first logical gate means connected for imparting a time delay to said first control signal when said inner selection signal is in the chip-selecting state; and second logical gate means connected to receive the delayed signal provided by said first logical gate means and the first control signal for effecting a logical disjunctive linkage of the delayed signal and the corresponding undelayed first control signal to thereby provide said second control signal.

Claim 10

A semiconductor memory as claimed in claim 7 wherein the inner selection signal has an associated chip-selecting state, and said memory cell array has a first group of lines constituting word lines and a second group of lines constituting column select lines, and further comprising a selection line control circuit for generating a selection line control signal for controlling at least one said group of lines, said selection line control circuit having means for placing said selection line control signal in a state to deactivate at least one of said groups of lines when said inner selection signal is in the chip-selecting state.

Claim 11

A semiconductor memory as claimed in claim 7 wherein the inner selection signal has an associated chip-selecting state and said first logical gate means are inhibited from producing an output when said inner selection signal is not in the chip-selecting state.

Claim 12

A semiconductor memory comprising: a memory cell array; an input terminal for receiving a chip selection signal; a control signal generating means connected for generating a first control signal at a first state immediately after said chip selection signal changes from a non-selecting state into a selecting state and at a second state for controlling the operation of said memory cell array in the selecting state; a signal changing means connected for producing from said first control signal a second control signal for controlling the operation of said memory cell array, wherein said signal changing means comprising: first means connected for producing a delayed first control signal whose termination is delayed relative to termination of the first control signal; and second means connected for causing said second control signal to terminate upon termination of said first control signal at the first state and for causing said second control signal to terminate upon termination of the delayed first control signal at the second state.

Claim 13

A semiconductor memory comprising: a memory cell array; an input terminal for receiving a chip selection signal; a control signal generating means connected for generating a first control signal at a first state immediately after said chip selection signal changes from a non-selecting state into a selecting state and at a second state for controlling the operation of said memory cell array in the selecting state; a signal changing means connected for producing from said first control signal a second control signal for controlling the operation of said memory cell array, wherein said signal changing means comprising: first means connected for producing a delayed first control signal whose termination is delayed relative to termination of the first control signal; and second means connected for causing said second control signal to terminate upon termination of said first control signal at the first state and for causing said second control signal to terminate upon termination of the delayed first control signal at the second state.

Claim 14

A semiconductor memory as claimed in claim 10 wherein said memory cell array has a pair of data lines, and said second control signal acts to equalize the pair of data lines of the memory cell array.

Claim 15

A semiconductor memory as claimed in claim 11 wherein said control signal generating means is connected for receiving address signals and the chip selection signal from the input terminal, for detecting a change of the received address signals, and for generating said first control signal in response to the change detected.

Claim 16

A semiconductor memory comprising: a memory cell array having word lines and data lines; input terminals for receiving a chip selection signal and address signals; a selection signal generating means connected for generating an inner selection signal in response to the chip selection signal, the inner selection signal having a selecting state and a non selecting state; a control signal generating means connected for detecting a change in the address signals and generating a control pulse having a predetermined duration in response to detecting the change in the address signals; a decoder connected to the word lines for selecting a word line based on the address signals; and means connected for inhibiting the operation of the decoder for selecting a word line during the predetermined duration in response to the control pulse, when the inner selection signal is in the selecting state.

Claim 17

A semiconductor memory comprising: a memory cell array having word lines and data lines; input terminals for receiving a chip selection signal and address signals; a selection signal generating means connected for generating an inner selection signal in response to the chip selection signal, the inner selection signal having a selecting state and a non selecting state; a control signal generating means connected for detecting a change in the address signals and generating a control pulse having a predetermined duration in response to detecting the change in the address signals; a decoder connected to the word lines for selecting a word line based on the address signals; and means connected for inhibiting the operation of the decoder for selecting a word line during the predetermined duration in response to the control pulse, when the inner selection signal is in the selecting state.

Claim 18

A semiconductor memory as claimed in claim 13 wherein said memory cell array has a pair data lines, and said control pulse acts to equalize the pair of date lines of the memory cell array.

Claim 19

A semiconductor memory as claimed in claim 14 wherein said control signal generating means is operative for further detecting a change of the chip selection and generating the control pulse in response to detecting the change of the chip selection signal, and said decoder does not inhibit the operation for selecting a word line in response to the control pulse when the inner selection signal is in the non-selecting state.