Semiconductor device having matched-timing dynamic circuit and static circuit

Claim 2

A semiconductor device comprising: a clock signal generating circuit (1) for generating a clock signal (0) by receiving an external signal (S); a multi-stage dynamic circuit (2) connected to said clock signal generating circuit (1) and initiated by said clock signal (φ); a delay circuit (5) of a static type, connected to said clock signal generating circuit (1) and to one stage of said multi-stage dynamic circuit (2), for delaying said clock signal (φ) and generating a delayed clock signal (Ø d ) ' said one stage of said multi-stage dynamic circuit (2) being initiated by said delayed clock signal (Ø d ); a static circuit (3) of a static type controlled by said external signal (S); and an output circuit (4), connected to said multi-stage dynamic circuit (2) and to said static circuit (3), for generating a signal (OUT) in response to the operation of said static circuit (3) matched by the operation of said multi-stage dynamic circuit (2).

Claim 3

A device as set forth in claim 1, wherein said delay circuit (5) is connected to the final stage (2-n) of said multi-stage dynamic circuit (2).

Claim 4

A device as set forth in claim 1, wherein said delay circuit (5) comprises: a first inverter (INV l ) connected to said clock signal generating circuit (1); a second inverter (INV 2 ), connected to said clock signal generating circuit (1) and to said first inverter (INV1), said second inverter (INV 2 ) having a load means (Q 54 ); a capacitor (C 3 ) connected to said second inverter (INV 2 ), said capacitor (C 3 ) being charged by said second inverter (INV 2 ) when the potential of said clock signal (φ) is at a first level, said capacitor (C 3 ) being discharged by said second inverter (INV 2 ) through said load means (Q 54 ) thereof when the potential of said clock signal (φ) is at a second level; and a third inverter (INV 3 ) connected to said capacitor (C 3 ), for generating said delayed clock signal (φ d ) .

Claim 5

A semiconductor device comprising: a plurality of address buffers (100) for receiving external address signals (A 0 -A 7 ) to generate internal address signals (A 0 -A 7 ) and their inverted internal address signals ( A 0 - A 7 ); an address transition detection circuit (101), connected to said address buffers (100), for detecting a transition in potential of said internal address signals (A 0 , A 0 -A 7 , A 7 ) to generate a clock signal (φ); a multi-stage dynamic circuit (102) connected to said address transition circuit (101), and initiated by said clock signal (φ); a delay circuit (105), connected to said address transition circuit (101) and to one stage of said multi-stage dynamic circuit (102), for delaying said clock signal (o) and generating a delayed clock signal (φ d ), said one stage of said multi-stage dynamic circuit (2) being initiated by said delayed clock signal (φ d ) ; a plurality of address decoders (103), connected to said address buffers (100), for decoding said internal address signals (A 0 , A 0 -A 7 , A 7 ); and drive circuits (104), connected to said multi-stage dynamic circuit (102) and to said address decoders (103), for generating an output signal in response to the operation of said address decoders (103) matched by the operation of said multi-stage dynamic circuit (102).

Claim 6

A semiconductor device comprising: a plurality of address buffers (100) for receiving external address signals (A 0 -A 7 ) to generate internal address signals (A 0 -A 7 ) and their inverted internal address signals ( A 0 - A 7 ); an address transition detection circuit (101), connected to said address buffers (100), for detecting a transition in potential of said internal address signals (A 0 , A 0 -A 7 , A 7 ) to generate a clock signal (φ); a multi-stage dynamic circuit (102) connected to said address transition circuit (101), and initiated by said clock signal (φ); a delay circuit (105), connected to said address transition circuit (101) and to one stage of said multi-stage dynamic circuit (102), for delaying said clock signal (o) and generating a delayed clock signal (φ d ), said one stage of said multi-stage dynamic circuit (2) being initiated by said delayed clock signal (φ d ) ; a plurality of address decoders (103), connected to said address buffers (100), for decoding said internal address signals (A 0 , A 0 -A 7 , A 7 ); and drive circuits (104), connected to said multi-stage dynamic circuit (102) and to said address decoders (103), for generating an output signal in response to the operation of said address decoders (103) matched by the operation of said multi-stage dynamic circuit (102).

Claim 7

A device as set forth in claim 4, wherein said delay circuit is connected to the final stage (2-n') of said multi-stage dynamic circuit (102).

Claim 8

A device as set forth in claim 4, wherein said delay circuit (105) comprises: a first inverter (INV1) connected to said address transition detection circuit (101); a second inverter (INV 2 ), connected to said address transition detection circuit (101) and to said first inverter (INV 1 ), said second inverter (INV 2 ) having a load means (Q54); a capacitor (C 3 ) connected to said second inverter (INV 2 ), said capacitor (C 3 ) being charged by said second inverter (INV 2 ) when the potential of said clock signal (φ) is at a first level, said capacitor (C 3 ) being discharged by said second inverter (INV 2 ) through said load means (Q 54 ) thereof when the potential of said clock signal (φ) is at a second level; and a third inverter (INV 3 ) connected to said capacitor (C 3 ), for generating said delayed clock signal (φ d ) .