Delay circuit for delaying differential signals includes separately controllable first and second load and clamp circuits for effecting different delay times

Claim 2

A delay circuit for delaying of differential signals, comprising a first input and a second input, a first output and a second output, a first current source, a first switching transistor and a second switching transistor each comprising a control electrode and a first main electrode and a second main electrode, the first input and the second input of the delay circuit being coupled to the control electrodes of the first switching transistor and the second switching transistor, respectively, the first main electrodes of the first switching transistor and the second switching transistor being coupled to one another and, via the first current source, to a first power supply terminal, the second main electrodes of the first switching transistor and the second switching transistor being coupled to the first output and the second output, respectively, of the delay circuit, the delay circuit further comprising first load circuits for coupling, respectively, the first output and the second output to a second power supply terminal, and respective first clamp circuits coupled to the first output and the second output for limiting differences between a voltage on the second power supply terminal and voltages on the first output and the second output, characterized in that the delay circuit comprises a second current source, second load circuits, second clamp circuits, and switching means for selectively connecting the second current source, the second load circuits and the second clamp circuits in parallel with the first current source, the first load circuits, and the first clamp circuits, respectively.

Claim 3

The delay circuit as claimed in claim 1, characterized in that the delay circuit is included in an integrated circuit in which substantially similar circuits are used for the first current source and the second current source, substantially similar circuits are used for the first load circuits and the second load circuits, and substantially similar circuits are used for the first clamp circuits and the second clamp circuits, wherein a ratio of the geometrical dimensions of the circuits of each pair are the same.

Claim 4

The delay circuit as claimed in claim 1, characterized in that the delay circuit comprises a third switching transistor and a fourth switching transistor, said third and fourth switching transistors having control electrodes and second main electrodes connected in parallel to the control electrodes and the second main electrodes of the first and second switching transistors, respectively, the third and fourth switching transistors also having first main electrodes coupled together and, separately from the first main electrodes of the first and second switching transistors, connected to the first power supply terminal via the second current source.

Claim 5

The delay circuit as claimed in claim 2, characterized in that the delay circuit comprises a third switching transistor and a fourth switching transistor, said third and fourth switching transistors having control electrodes and second main electrodes connected in parallel to the control electrodes and the second main electrodes of the first and second switching transistors, respectively, the third and fourth switching transistors also having first main electrodes coupled together and, separately from the first main electrodes of the first and second switching transistors, connected to the first power supply terminal via the second current source.

Claim 6

A delay circuit as claimed in claim 1, characterized in that the delay circuit comprises, between the first current source and the first output, a parallel connection of a first and a second series connection of main current paths between first and second main electrodes of transistors, the first switching transistor forming part of the first series connection, the transistors of said first series connection having control electrodes which are coupled to the first input and a first selection input, respectively, the transistors of said second series connection having control electrodes which are coupled to a further first input and a second selection input, respectively, and in that the delay circuit comprises a third and a fourth series connection of main current paths between first and second main electrodes of transistors, connected in parallel between the second current source and the second output, the second switching transistor forming part of the third series connection, the transistors of said third series connection having control electrodes which are coupled to the second input and the first selection input, respectively, the transistors of the fourth series connection having control electrodes which are coupled to a further second input and the second selection input, respectively.

Claim 7

The delay circuit as claimed in claim 2, characterized in that the delay circuit comprises, between the current source and the first output, a parallel connection of a first and a second series connection of main current paths between first and second main electrodes of transistors, the first switching transistor forming part of the first series connection, the transistors of said first series connection having control electrodes which are coupled to the first input and a first selection input, respectively, the transistors of the second series connection having control electrodes which are coupled to a further first input and a second selection input, respectively, and in that the delay circuit comprises a third and a fourth series connection of main current paths between first and second main electrodes of transistors, connected in parallel between the second current source and the second output, the second switching transistor forming part of the third series connection, the transistors of said third series connection having control electrodes which are coupled to the second input and the first selection input, respectively, the transistors of the fourth series connection having control electrodes which are coupled to a further second input and the second selection input, respectively.

Claim 8

The delay circuit as claimed in claim 3, characterized in that the delay circuit comprises, between the current source and the first output, a parallel connection of a first and a second series connection of main current paths between first and second main electrodes of transistors, the first switching transistor forming part of the first series connection, the transistors of said first series connection having control electrodes which are coupled to the first input and a first selection input, respectively, the transistors of said second series connection having control electrodes which are coupled to a further first input and a second selection input, respectively, and in that the delay circuit comprises a third and a fourth series connection of main current paths between first and second main electrodes of transistors, connected in parallel between the second current source and the second output, the second switching transistor forming part of the third series connection, the transistors of the third series connection having control electrodes which are coupled to the second input and the first selection input, respectively, the transistors of said fourth series connection having control electrodes which are coupled to a further second input and the second selection input, respectively.

Claim 9

The delay circuit as claimed in claim 4, characterized in that the delay circuit comprises, between the current source and the first output, a parallel connection of a first and a second series connection of main current paths between first and second main electrodes of transistors, the first switching transistor forming part of the first series connection, the transistors of said first series connection having control electrodes which are coupled to the first input and a first selection input, respectively, the transistors of said second series connection having control electrodes which are coupled to a further first input and a second selection input, respectively, and in that the delay circuit comprises a third and a fourth series connection of main current paths between first and second main electrodes of transistors, connected in parallel between the second current source and the second output, the second switching transistor forming part of the third series connection, the transistors of said third series connection having control electrodes which are coupled to the second input and the first selection input, respectively, the transistors of said fourth series connection having control electrodes which are coupled to a further second input and the second selection input, respectively.

Claim 10

The delay circuit as claimed in claim 1, characterized in that the respective first load circuits are constructed as current controllers which are adapted to draw substantially half the amount of current supplied by the current source.

Claim 11

The delay circuit as claimed in claim 1, characterized in that the respective clamp circuits each comprises a clamp transistor which is coupled to the respective output by a first main electrode, and a control electrode of said clamp transistor receiving a reference voltage.

Claim 12

A cascade of delay circuits, each of said delay circuits being suitable for delaying differential signals, each of said delay circuits comprising a first input and a second input, a first output and a second output, a first current source, a first switching transistor and a second switching transistor each comprising a control electrode and a first main electrode and a second main electrode, the first input and the second input of the delay circuit being coupled to the control electrodes of the first switching transistor and the second switching transistor, respectively, the first main electrodes of the first switching transistor and the second switching transistor being coupled to one another and, via the first current source, to a first power supply terminal, the second main electrodes of the first switching transistor and the second switching transistor being coupled to the first output and the second output, respectively, of the delay circuit, each delay circuit further comprising first load circuits for coupling, respectively, the first output and the second output to a second power supply terminal, and respective first clamp circuits coupled to the first output and the second output for limiting differences between a voltage on the second power supply terminal and voltages on the first output and the second output, characterized in that each delay circuit comprises a second current source, second load circuits, second clamp circuits, and switching means for selectively connecting the second current source, the second load circuits and the second clamp circuits in parallel with the first current source, the first load circuits, and the first clamp circuits, respectively.

Claim 13

A cascade of delay circuits, each of said delay circuits being suitable for delaying differential signals, each of said delay circuits comprising a first input and a second input, a first output and a second output, a first current source, a first switching transistor and a second switching transistor each comprising a control electrode and a first main electrode and a second main electrode, the first input and the second input of the delay circuit being coupled to the control electrodes of the first switching transistor and the second switching transistor, respectively, the first main electrodes of the first switching transistor and the second switching transistor being coupled to one another and, via the first current source, to a first power supply terminal, the second main electrodes of the first switching transistor and the second switching transistor being coupled to the first output and the second output, respectively, of the delay circuit, each delay circuit further comprising first load circuits for coupling, respectively, the first output and the second output to a second power supply terminal, and respective first clamp circuits coupled to the first output and the second output for limiting differences between a voltage on the second power supply terminal and voltages on the first output and the second output, characterized in that each delay circuit comprises a second current source, second load circuits, second clamp circuits, and switching means for selectively connecting the second current source, the second load circuits and the second clamp circuits in parallel with the first current source, the first load circuits, and the first clamp circuits, respectively.

Claim 14

The cascade of delay circuits as claimed in claim 11, wherein at least one of said delay circuits comprises, between the first current source and the first output, a parallel connection of a first and a second series connection of main current channels of transistors, the first switching transistor forming part of the first series connection having control electrodes which are coupled to the first input and a first selection input, respectively, the second series connection having control electrodes which are coupled to a further first input and a second selection input, respectively, and in that the delay circuit comprises a third and a fourth series connection of main current channels of transistors, connected in parallel between the'second current source and the second output, the second switching transistor forming part of the third series connection with control electrodes which are coupled to the second input and the first selection input, respectively, the fourth series connection comprising control electrodes which are coupled to a further second input and the second selection input, respectively, characterized in that the outputs of one of the delay circuits, secondly preceding said at least one delay circuit, are connected to the further first and second input of said at least one delay circuit.

Claim 15

The cascade of delay circuits as claimed in claim 11, characterized in that the outputs of a last delay circuit in the cascade of delay circuits are coupled back to the inputs of a first delay circuit in the cascade of delay circuits so that a loop gain of the cascade of delay circuits is negative.

Claim 16

The cascade of delay circuits as claimed in claim 12, characterized in that the outputs of a last delay circuit in the cascade of delay circuits are coupled back to the inputs of a first delay circuit in the cascade of delay circuits so that a loop gain of the cascade of delay circuits is negative.