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US5473181A
Expired / Lapsed
US
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Integrated circuit arrangement having at least one power component and low-voltage components
Assignee: Infineon Technologies AG
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Filing: 1994-09-29
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Granted: 1995-12-05
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Expires: 2014-09-29
Abstract
Abstract In an integrated circuit arrangement having at least one power component and low-voltage components, the at least one power component is realized in a semiconductor substrate. At least one contact of the power component is arranged on a principal surface of the substrate. The contact is covered with an insulation layer at a surface of which at least one thin-film component, particularly a thin-film transistor, is provided above the contact.
Inventors
- 👤 Udo Schwalke
- 👤 Michael Stoisiek
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:13
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/66; H10D88/00
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
151 words
An integrated circuit arrangement, comprising: at least one power component and a low-voltage component; said at least one power component being integrated in a semiconductor substrate; at least one contact of the power component being arranged on a principle surface of the substrate and a connection contact level connected to the contact and which extends across and above said principle surface; an insulating layer covering the connection contact level; and at least one thin-film component formed of one of the elements selected from the group consisting of an amorphous semiconductor material and a polycrystalline semiconductor material as said low-voltage component positioned above the connection contact level and the at least one power component so that the connection contact level lies between the at least one power component and the at least one thin-film component so that the connection contact level shields the thin-film component against electrical fields occurring in the substrate.
Claim 2
Dependent Claim
151 words
An integrated circuit arrangement, comprising: at least one power component and a low-voltage component; said at least one power component being integrated in a semiconductor substrate; at least one contact of the power component being arranged on a principle surface of the substrate and a connection contact level connected to the contact and which extends across and above said principle surface; an insulating layer covering the connection contact level; and at least one thin-film component formed of one of the elements selected from the group consisting of an amorphous semiconductor material and a polycrystalline semiconductor material as said low-voltage component positioned above the connection contact level and the at least one power component so that the connection contact level lies between the at least one power component and the at least one thin-film component so that the connection contact level shields the thin-film component against electrical fields occurring in the substrate.
Claim 3
Dependent Claim
64 words
A circuit arrangement according to claim 1 wherein: the power component is MOS-controlled; the power component comprises a source region that adjoins the principal surface and comprises a source electrode as said at least one contact that is arranged on the principal surface; and the thin-film component being arranged above the source electrode that is insulated from the thin-film component by the insulation layer.
Claim 4
Dependent Claim
122 words
A circuit arrangement according to claim 2 wherein: the power component comprises a cell structure, a plurality of source regions at the principal surface and each of which adjoins at a respective channel region, and the channel regions also adjoining the principal surface, a gate dielectric and a gate electrode arranged over the principal surface; the gate electrodes being connected to one another via a gate connection level; the source electrodes being arranged on the principal surface and connected to one another via said connection contact level; and an insulating layer arranged between the gate electrodes and the connection contact level, said insulating layer insulating the gate electrodes and the gate connection level from the source electrodes and the connection contact level.
Claim 5
Dependent Claim
28 words
A circuit arrangement according to claim 3 wherein the source electrodes and the connection contact level are formed of a high-temperature-resistant conductor as a continuous source metallization level.
Claim 6
Dependent Claim
16 words
A circuit arrangement according to claim 4 wherein the source metallization level is formed of tungsten.
Claim 7
Dependent Claim
18 words
A circuit arrangement according to claim 4 wherein the source metallization level is formed of a metal silicide.
Claim 8
Dependent Claim
25 words
A circuit arrangement according to claim 1 wherein the insulation layer covering the contact comprises a planar surface on which the thin-film component is arranged.
Claim 9
Dependent Claim
19 words
A circuit arrangement according to claim 1 wherein at least one thin-film transistor is provided as a thin-film component.
Claim 10
Dependent Claim
118 words
An integrated circuit arrangement, comprising: at least one power component integrated in a semiconductor substrate; said power component having a region at a principal surface of the substrate to which is connected a contact metallization level which runs laterally over the principal surface of the substrate and over the at least one power component; an insulation layer on the contact metallization level; and a thin film component on the insulation layer above the at least one power component, the contact metallization level being positioned between the thin film component and the at least one power component so that it shields the thin-film component against electrical fields occurring in the substrate associated with the at least one power component.
Claim 11
Dependent Claim
118 words
An integrated circuit arrangement, comprising: at least one power component integrated in a semiconductor substrate; said power component having a region at a principal surface of the substrate to which is connected a contact metallization level which runs laterally over the principal surface of the substrate and over the at least one power component; an insulation layer on the contact metallization level; and a thin film component on the insulation layer above the at least one power component, the contact metallization level being positioned between the thin film component and the at least one power component so that it shields the thin-film component against electrical fields occurring in the substrate associated with the at least one power component.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-12-04 | 1999-06-05 | 1999-12-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-12-04 | 2003-06-05 | 2003-12-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-12-04 | 2007-06-05 | 2007-12-05 | $7700.00 | Window Closed / Lapsed |