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US5470790A Expired / Lapsed US ⏱️ 0.0 years remaining

Via hole profile and method of fabrication

Assignee: Intel Corp
•
Filing: 1994-10-17
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Granted: 1995-11-28
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Expires: 2014-10-17
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Abstract

Abstract A novel high performance and reliable interconnection structure for preventing via delamination. The interconnection structure of the present invention comprises a via connection which extends into and undercuts an underlying interconnection line to lock the via connection into the interconnection line.

Inventors

  • 👤 Alan M. Myers
  • 👤 Peter K. Charvat
  • 👤 Thomas A. Letson
  • 👤 Shi-Ning Yang
  • 👤 Peng Bai

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 06:00
CPC Classifications
H; H10; H10P; H10P50/00; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; H10W20/083; H10P50/20; H10P50/26; H10P50/264; H10P50/60; H10P50/66; H10P50/663; H10P50/667; H10W20/031; H10W20/063; H10W20/0633; H10W20/40; H10W20/41; H10W20/42; H10W20/425; H10W20/438; Y; Y10; Y10S; Y10S257/00; Y10S257/915

Claims Analysis

Total Claims: 17
Claim 1
Independent Claim 89 words
A method of forming an interconnection structure of an integrated circuit formed on a semiconductor substrate comprising the steps of: forming a first conductive layer above said substrate; forming a second conductive layer on said first conductive layer; forming an insulating layer over said second conductive layer; forming a first opening through said insulating layer, and said second conductive layer; and forming a second opening in said first conductive layer beneath said first opening wherein said second opening is wider than said first opening in said second conductive layer.
Claim 2
Independent Claim 89 words
A method of forming an interconnection structure of an integrated circuit formed on a semiconductor substrate comprising the steps of: forming a first conductive layer above said substrate; forming a second conductive layer on said first conductive layer; forming an insulating layer over said second conductive layer; forming a first opening through said insulating layer, and said second conductive layer; and forming a second opening in said first conductive layer beneath said first opening wherein said second opening is wider than said first opening in said second conductive layer.
Claim 3
Dependent Claim 31 words
The method of claim 1 wherein said second opening is formed by etching with an etchant which is selective to said first conductive layer with respect to said second conductive layer.
Claim 4
Dependent Claim 12 words
The method of claim 2 wherein said etchant is a wet etchant.
Claim 5
Dependent Claim 72 words
The method of claim 3 wherein said step of forming said second opening comprises the steps of: exposing said substrate to a solution comprising approximately 40-60 weight percent of 1-methyl-2-pyrrolidinone, 30-50 weight percent sulfolane, and 5-15 weight percent menoisopropanolamine. exposing said substrate to a solution comprising water; after exposing said substrate to said solution comprising water, letting said substrate sit for a period of time; rinsing said substrate; and drying said substrate.
Claim 6
Dependent Claim 15 words
The method of claim 1 wherein said first conductive layer is an aluminum alloy layer.
Claim 7
Dependent Claim 17 words
The method of claim 1 wherein said second conductive layer is a refractory metal aluminum compound layer.
Claim 8
Dependent Claim 13 words
The method of claim 6 wherein said second conductive layer is titanium aluminide.
Claim 9
Dependent Claim 66 words
The method of claim 7 wherein said first conductive layer is an aluminum alloy layer and said step of forming said second conductive layer comprises the steps of: forming a titanium layer on said aluminum alloy layer; and heating said aluminum alloy layer and said titanium layer until substantially all of said titanium layer reacts with said aluminum alloy layer to form said titanium aluminide layer.
Claim 10
Dependent Claim 23 words
The method of claim 1 further comprising the step of forming a titanium layer beneath said first conductive layer and above said substrate.
Claim 11
Dependent Claim 17 words
The method of claim 1 wherein said second opening extends only partially through said first conductive layer.
Claim 12
Dependent Claim 70 words
A process for forming an interconnection structure of an integrated circuit comprising the steps of: forming an interconnection; etching said interconnection a first time to form a first opening having a first width in said interconnection; and etching said interconnection a second time beneath said first opening such that said interconnection is etched laterally to form a second opening which extends laterally further into said interconnection than said first opening.
Claim 13
Dependent Claim 70 words
A process for forming an interconnection structure of an integrated circuit comprising the steps of: forming an interconnection; etching said interconnection a first time to form a first opening having a first width in said interconnection; and etching said interconnection a second time beneath said first opening such that said interconnection is etched laterally to form a second opening which extends laterally further into said interconnection than said first opening.
Claim 14
Dependent Claim 33 words
The process of claim 11 wherein said first etch forms said first opening through a conductive capping layer of said interconnection, and wherein said second etch etches laterally beneath said conductive capping layer.
Claim 15
Dependent Claim 13 words
The process of claim 12 wherein said first etch is a dry etch.
Claim 16
Dependent Claim 13 words
The process of claim 12 wherein said second etch is a wet etch.
Claim 17
Dependent Claim 24 words
The process of claim 12 wherein said conductive capping layer of said interconnection comprises titanium aluminide and wherein said interconnection comprises an aluminum alloy.

References Cited (Backward Citations)

US4507852A Cited
US4714686A Cited
JPS63133647A Cited
US4879257A Cited
JPH02122546A Cited
US5106461A Cited
US5312775A Cited
US5408130A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-11-27 1999-05-29 1999-11-28 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-11-27 2003-05-29 2003-11-28 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-11-27 2007-05-29 2007-11-28 $7700.00 Window Closed / Lapsed

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