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US5469100A Expired / Lapsed US ⏱️ 0.0 years remaining

Circuit for the generation of a time-stabilized output pulse

Assignee: STMicroelectronics SA
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Filing: 1994-06-16
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Granted: 1995-11-21
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Expires: 2014-06-16
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Abstract

Abstract A circuit for the generation of a time-stabilized output pulse Iout comprises a capacitor biased by two completely independent voltages whose bias voltages are fixed by a current generator through current mirrors and are therefore very stable.

Inventors

  • 👤 Sylvie Wuidart
  • 👤 Tien-Dung Do

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 12:24
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/355; H03K5/00; H03K5/01; H03K5/04

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 255 words
A generation circuit to generate a time-stabilized output pulse, of a type comprising a capacitor connected, firstly, to a charging circuit and, secondly, to a discharging circuit, said charging and discharging circuits being controlled by an input pulse, wherein said generation circuit comprises a comparator constituted by: a first transistor biased by said capacitor, the capacitor being, firstly, discharged through the discharging circuit for a first level of the input pulse and, secondly, charged for a second level of the input pulse, through the charging circuit at a fixed current given by a first current mirror of a current generator, a second transistor in series with the first transistor, said second transistor being, firstly, turned off for the first level of the input pulse and, secondly, biased for the second level of the input pulse by a fixed bias voltage defined by a current given by a second current mirror of said current generator, said comparator delivering an output signal having, for the second level of the input pulse, a component with a variable level, corresponding to a charge of the capacitor, variations of this component being defined by a value of the charging current of the capacitor and by the bias voltage of the second transistor so that, said output signal of the comparator being applied to logic means of comparison of the input pulse, a duration of output pulse of the logic means is determined by said value of the charging current of the capacitor and said bias voltage of the second transistor.
Claim 2
Dependent Claim 255 words
A generation circuit to generate a time-stabilized output pulse, of a type comprising a capacitor connected, firstly, to a charging circuit and, secondly, to a discharging circuit, said charging and discharging circuits being controlled by an input pulse, wherein said generation circuit comprises a comparator constituted by: a first transistor biased by said capacitor, the capacitor being, firstly, discharged through the discharging circuit for a first level of the input pulse and, secondly, charged for a second level of the input pulse, through the charging circuit at a fixed current given by a first current mirror of a current generator, a second transistor in series with the first transistor, said second transistor being, firstly, turned off for the first level of the input pulse and, secondly, biased for the second level of the input pulse by a fixed bias voltage defined by a current given by a second current mirror of said current generator, said comparator delivering an output signal having, for the second level of the input pulse, a component with a variable level, corresponding to a charge of the capacitor, variations of this component being defined by a value of the charging current of the capacitor and by the bias voltage of the second transistor so that, said output signal of the comparator being applied to logic means of comparison of the input pulse, a duration of output pulse of the logic means is determined by said value of the charging current of the capacitor and said bias voltage of the second transistor.
Claim 3
Dependent Claim 20 words
A generation circuit according to claim 1, wherein said current generator comprises by a control transistor mounted as a diode.
Claim 4
Dependent Claim 36 words
A generation circuit according to claim 1, wherein said bias voltage of the second transistor of the comparator is a threshold voltage of a bias transistor supplied with the current given by the second current mirror.
Claim 5
Dependent Claim 23 words
A generation circuit according to claims 1, wherein the first and second current mirrors each comprise a transistor biased by said control transistor.

References Cited (Backward Citations)

DE2620187A1 Cited
FR2310658A1 Cited
US4047057A Cited
EP0015364A1 Cited
US4305010A Cited
US4421994A Cited
EP0405319A1 Cited
US5057722A Cited
US5081380A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-11-20 1999-05-22 1999-11-21 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-11-20 2003-05-22 2003-11-21 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-11-20 2007-05-22 2007-11-21 $7700.00 Window Closed / Lapsed

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