Delay circuit having stable delay time

Claim 2

A delay circuit comprising: an input terminal and an output terminal; a first MOSFET having a gate connected to the input terminal, and a drain-source path connected at its one end to a first node and at its other end to a first voltage supply line; a second MOSFET having a gate connected to the first node and a drain-source path connected at its one end to the first node and at its other end to the first voltage supply line; a third MOSFET having a gate connected to the input terminal, and a drain-source path connected at its one end through a first resistive element to the first node and at its other end to a second voltage supply line; a fourth MOSFET having a gate connected to the first node, and a drain-source path connected at its one end to a second node and at its other end to the first voltage supply line; a capacitive element connected between the second node and one of said first and second voltage supply lines; a fifth MOSFET having a gate connected to receive an inverted signal of a signal applied on the input terminal, and a drain-source path connected at its one end to the second node and at its other end to the second voltage supply line; a sixth MOSFET having a gate connected to the second node, and a drain-source path connected at its one end to the output terminal and at its other end to the first voltage supply line; and a seventh MOSFET having a gate connected to the input terminal, and a drain-source path connected at its one end through a second resistive element to the output terminal and at its other end to the second voltage supply line.

Claim 3

A circuit claimed in claim 1 wherein the capacitive element is connected between the second node and the second voltage supply line.

Claim 4

A circuit claimed in claim 1 wherein the capacitive element is connected between the second node and the first voltage supply line.

Claim 5

A delay circuit comprising: an input terminal and an output terminal; a first MOSFET of a first channel type having a gate connected to the input terminal, a drain connected to a first node and a source connected to a first voltage supply line; a second MOSFET of the first channel type having a gate and a drain connected commonly to the first node and a source connected to the first voltage supply line; a third MOSFET of a second channel type having a gate connected to the input terminal, a drain connected through a first resistor to the first node and a source connected to a second voltage supply line; a fourth MOSFET of the first channel type having a gate connected to the first node, a drain connected to a second node and a source connected to the first voltage supply line; a capacitor connected between the second node and one of said first and second voltage supply lines; a fifth MOSFET of the second channel type having a gate connected to receive an inverted signal of a signal applied on the input terminal, a drain connected to the second node and a source connected to the second voltage supply line; a sixth MOSFET of the first channel type having a gate connected to the second node, a drain connected to the output terminal and a source connected to the first voltage supply line; and a seventh MOSFET of the second channel type having a gate connected to the input terminal, a drain connected through a second resistor to the output terminal and a source connected to the second voltage supply line, the second and fourth MOSFETs forming a current mirror circuit, and transconductances of the second, third, sixth and seventh MOSFETs and resistances of the first and second resistors fulfilling the following conditions: g.sub.m2 =n×g.sub.m6 g.sub.m3 =n×g.sub.m7 R.sub.1 =R.sub.2 /n where g m2 , g m3 , g m6 and g m7 are transconductances of the second, third, sixth and seventh MOSFETs, respectively, R 1 and R 2 are resistances of the first and second resistors, respectively, and n is positive number.

Claim 6

A delay circuit comprising: an input terminal and an output terminal; a first MOSFET of a first channel type having a gate connected to the input terminal, a drain connected to a first node and a source connected to a first voltage supply line; a second MOSFET of the first channel type having a gate and a drain connected commonly to the first node and a source connected to the first voltage supply line; a third MOSFET of a second channel type having a gate connected to the input terminal, a drain connected through a first resistor to the first node and a source connected to a second voltage supply line; a fourth MOSFET of the first channel type having a gate connected to the first node, a drain connected to a second node and a source connected to the first voltage supply line; a capacitor connected between the second node and one of said first and second voltage supply lines; a fifth MOSFET of the second channel type having a gate connected to receive an inverted signal of a signal applied on the input terminal, a drain connected to the second node and a source connected to the second voltage supply line; a sixth MOSFET of the first channel type having a gate connected to the second node, a drain connected to the output terminal and a source connected to the first voltage supply line; and a seventh MOSFET of the second channel type having a gate connected to the input terminal, a drain connected through a second resistor to the output terminal and a source connected to the second voltage supply line, the second and fourth MOSFETs forming a current mirror circuit, and transconductances of the second, third, sixth and seventh MOSFETs and resistances of the first and second resistors fulfilling the following conditions: g.sub.m2 =n×g.sub.m6 g.sub.m3 =n×g.sub.m7 R.sub.1 =R.sub.2 /n where g m2 , g m3 , g m6 and g m7 are transconductances of the second, third, sixth and seventh MOSFETs, respectively, R 1 and R 2 are resistances of the first and second resistors, respectively, and n is positive number.

Claim 7

A circuit claimed in claim 4 wherein the first channel type is a P-channel type and the second channel type is an N-channel type.

Claim 8

A circuit claimed in claim 5 wherein the capacitor is connected between the second node and the second voltage supply line.

Claim 9

A circuit claimed in claim 5 wherein the capacitor is connected between the second node and the first voltage supply line.

Claim 10

A delay circuit comprising: an input terminal and an output terminal; a first inverter including a first MOSFET of a first channel type having a gate connected to the input terminal, a drain connected to a first node and a source connected to a first voltage supply line; and a second MOSFET of a second channel type having a gate connected to the input terminal, a drain connected through a first resistor to the first node and a source connected to a second voltage supply line; a current mirror circuit having an input side current path connected in parallel to the first MOSFET, and an output side current path connected between the first voltage supply line and a second node; a capacitor connected between the second node and one of said first and second voltage supply lines; a third MOSFET of the second channel type having a gate connected to receive an inverted signal of a signal applied on the input terminal, a drain connected to the second node and a source connected to the second voltage supply line; and a second inverter including a fourth MOSFET of the first channel type having a gate connected to the second node, a drain connected to the output terminal and a source connected to the first voltage supply line, and a fifth MOSFET of the second channel type having a gate connected to the input terminal, a drain connected through a second resistor to the output terminal and a source connected to the second voltage supply line.

Claim 11

A delay circuit comprising: an input terminal and an output terminal; a first inverter including a first MOSFET of a first channel type having a gate connected to the input terminal, a drain connected to a first node and a source connected to a first voltage supply line; and a second MOSFET of a second channel type having a gate connected to the input terminal, a drain connected through a first resistor to the first node and a source connected to a second voltage supply line; a current mirror circuit having an input side current path connected in parallel to the first MOSFET, and an output side current path connected between the first voltage supply line and a second node; a capacitor connected between the second node and one of said first and second voltage supply lines; a third MOSFET of the second channel type having a gate connected to receive an inverted signal of a signal applied on the input terminal, a drain connected to the second node and a source connected to the second voltage supply line; and a second inverter including a fourth MOSFET of the first channel type having a gate connected to the second node, a drain connected to the output terminal and a source connected to the first voltage supply line, and a fifth MOSFET of the second channel type having a gate connected to the input terminal, a drain connected through a second resistor to the output terminal and a source connected to the second voltage supply line.