US5469097A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Translator circuit with symmetrical switching delays
Assignee: Advanced Micro Devices Inc
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Filing: 1995-05-10
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Granted: 1995-11-21
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Expires: 2015-05-10
Abstract
Abstract A translator circuit for providing symmetrical switching delays for use with a power line for a differential amplifier having a first signal line and a complementary second signal line, the translator circuit including: a first voltage clamp coupled to the first signal line and to the power line for limiting a voltage differential between the power line and the first signal line; and a second voltage clamp coupled to the power line and the second signal line for limiting a voltage differential between the power line and the second signal line. The translator circuit provides reduced sensitivity to variations in process parameters, power supply voltages, temperature and manufacturing tolerances. The translator circuit also provides symmetrical tracking between the rise to rise and the fall to fall delays of an emitter coupled logic to complementary metal-oxide semiconductor translator circuit.
Inventors
- 👤 Kenneth Ho
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 15:22
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/086; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521; H03K19/018528; H03K19/003; H03K19/00369; H03K19/00384
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
158 words
A translator circuit for providing symmetrical switching delays having a differential amplifier including a first signal line and a second signal line complementary to the first signal, the circuit comprising a first voltage clamp means coupled to the first signal line and to the second signal line for limiting a voltage differential between the first signal line and the second signal line, the first voltage clamp including: a first pair of p-n diodes coupled in series between the first signal line and the second signal line for limiting the voltage differential between the first signal line and the second signal line; and a second pair of p-n diodes coupled in series between the second signal line and the first signal line for limiting the voltage differential between the second signal line and the first signal line wherein the first and second pair of p-n diodes further increase symmetry in rise and fall delays output from the translator circuit.
Claim 2
Dependent Claim
158 words
A translator circuit for providing symmetrical switching delays having a differential amplifier including a first signal line and a second signal line complementary to the first signal, the circuit comprising a first voltage clamp means coupled to the first signal line and to the second signal line for limiting a voltage differential between the first signal line and the second signal line, the first voltage clamp including: a first pair of p-n diodes coupled in series between the first signal line and the second signal line for limiting the voltage differential between the first signal line and the second signal line; and a second pair of p-n diodes coupled in series between the second signal line and the first signal line for limiting the voltage differential between the second signal line and the first signal line wherein the first and second pair of p-n diodes further increase symmetry in rise and fall delays output from the translator circuit.
Claim 3
Dependent Claim
21 words
The translator circuit of claim 1 wherein the first signal line and the second signal line are complementary metal-oxide semiconductor compatible.
Claim 4
Dependent Claim
115 words
A translator circuit for providing symmetrical switching delays having a differential amplifier including a first signal line and a second signal line complementary to the first signal and for use with a power line, the circuit comprising: first voltage clamp means coupled to the first signal line and to the power line for limiting a voltage differential therebetween; second voltage clamp means coupled to the power line and the second signal line for limiting a voltage differential therebetween; and third voltage clamp means coupled to the first signal line and to the second signal line for limiting a voltage differential therebetween and for increasing symmetry in rise and fall delays output from the translator circuit.
Claim 5
Dependent Claim
115 words
A translator circuit for providing symmetrical switching delays having a differential amplifier including a first signal line and a second signal line complementary to the first signal and for use with a power line, the circuit comprising: first voltage clamp means coupled to the first signal line and to the power line for limiting a voltage differential therebetween; second voltage clamp means coupled to the power line and the second signal line for limiting a voltage differential therebetween; and third voltage clamp means coupled to the first signal line and to the second signal line for limiting a voltage differential therebetween and for increasing symmetry in rise and fall delays output from the translator circuit.
Claim 6
Dependent Claim
21 words
The translator circuit of claim 3 wherein the first signal line and the second signal line are complementary metal-oxide semiconductor compatible.
Claim 7
Dependent Claim
55 words
The translator circuit of claim 4 wherein the first voltage clamp means further includes: a first transistor having a drain and a gate coupled to the power line; and a second transistor having a drain and a gate coupled to a source of the first transistor and a source coupled to the first signal line.
Claim 8
Dependent Claim
55 words
The translator circuit of claim 5 wherein the second voltage clamp means further includes: a third transistor having a drain and a gate coupled to the power line; and a fourth transistor having a drain and a gate coupled to a source of the third transistor and a source coupled to the second signal line.
Claim 9
Dependent Claim
83 words
The translator circuit of claim 6 wherein the third voltage clamp means further includes: a first pair of p-n diodes coupled in series between the first signal line and the second signal line for limiting the voltage differential between the first signal line and the second signal line; and a second pair of p-n diodes coupled in series between the second signal line and the first ,signal line for limiting the voltage differential between the second signal line and the first signal line.
Claim 10
Dependent Claim
93 words
The translator circuit of claim 7 further comprising: first switch means coupled to the first signal line and coupled to and responsive to the second signal line for providing an active load and for coupling the first signal line to the power line in response to the second signal line; and second switch means coupled to the second signal line and coupled to and responsive to the first signal line for providing an active load and for coupling the second signal line to the power line in response to the first signal line.
Claim 11
Dependent Claim
46 words
The translator circuit of claim 8 wherein the first switch means further comprises a fifth transistor having a source coupled to the first signal line, having a gate coupled to and responsive to the second signal line, and having a drain coupled to the power line.
Claim 12
Dependent Claim
46 words
The translator circuit of claim 9 wherein the second switch means further comprises a sixth transistor having a source coupled to the second signal line, having a gate coupled to and responsive to the first signal line, and having a drain coupled to the power line.
Claim 13
Dependent Claim
80 words
The translator circuit of claim 10 further comprising: a seventh transistor having a gate coupled to the second signal line, and a drain coupled to the power line; an eighth transistor having a source coupled to a lower power voltage; a resistive load coupled between the power line and a drain and a gate of the eighth transistor; and a resistive load coupled between a source of the seventh transistor and the drain and the gate of the eighth transistor.
Claim 14
Dependent Claim
90 words
The translator circuit of claim 11 further comprising: a ninth transistor having a gate coupled to the source and the drain of the eighth transistor, and a source coupled to the lower power voltage; and a tenth transistor having a drain coupled to the power line, a gate coupled to the first signal line, and a source coupled to the drain of the ninth transistor; wherein the source of the tenth transistor and the drain of the ninth transistor is an output signal line which is complementary metal-oxide semiconductor compatible.
Claim 15
Dependent Claim
43 words
The translator circuit of claim 12 further comprising: two differential emitter coupled logic signal lines; and down converter means coupled to the differential amplifier and to the differential emitter coupled logic signal lines for level shifting the differential emitter coupled logic signal lines.
Claim 16
Dependent Claim
23 words
The translator circuit of claim 13 wherein the differential amplifier means further comprises a first current source coupled to a lower power voltage.
Claim 17
Dependent Claim
21 words
The translator circuit of claim 14 further comprising: second current source means for providing current coupled to the down converter means.
Claim 18
Dependent Claim
145 words
A translator circuit having symmetrical switching delays for generating an output signal which is complementary metal-oxide semiconductor compatible having a differential amplifier responsive to differential input emitter coupled logic signals for generating a first signal and a second signal complementary to the first signal, the translator comprising: first voltage clamp means coupled to an upper power voltage and to the first signal for limiting voltage differential between the upper power voltage and the first signal; second voltage clamp means coupled to the upper power voltage and to the second signal for limiting a voltage differential between the upper power voltage and the second signal; and third voltage clamp means coupled to the first signal and to the second signal for limiting a voltage differential therebetween and for increasing symmetry in rise and fall delays between the input emitter coupled logic signals and the output signal.
Claim 19
Dependent Claim
145 words
A translator circuit having symmetrical switching delays for generating an output signal which is complementary metal-oxide semiconductor compatible having a differential amplifier responsive to differential input emitter coupled logic signals for generating a first signal and a second signal complementary to the first signal, the translator comprising: first voltage clamp means coupled to an upper power voltage and to the first signal for limiting voltage differential between the upper power voltage and the first signal; second voltage clamp means coupled to the upper power voltage and to the second signal for limiting a voltage differential between the upper power voltage and the second signal; and third voltage clamp means coupled to the first signal and to the second signal for limiting a voltage differential therebetween and for increasing symmetry in rise and fall delays between the input emitter coupled logic signals and the output signal.
Claim 20
Dependent Claim
180 words
The translator circuit of claim 16 wherein: the first voltage clamp means further includes a first transistor having a drain and a gate coupled to the power line and a second transistor having a drain and a gate coupled to a source of the first transistor and a source coupled to the first signal line; the second voltage clamp means further includes a third transistor having a drain and a gate coupled to the power line and a fourth transistor having a drain and a gate coupled to a source of the third transistor and a source coupled to the second signal line; and the third voltage clamp means further includes a first pair of p-n diodes coupled in series between the first signal line and the second signal line for limiting the voltage differential between the first signal line and the second signal line and a second pair of p-n diodes coupled in series between the second signal line and the first signal line for limiting the voltage differential between the second signal line and the first signal line.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-11-20 | 1999-05-22 | 1999-11-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-11-20 | 2003-05-22 | 2003-11-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-11-20 | 2007-05-22 | 2007-11-21 | $7700.00 | Window Closed / Lapsed |