Emitter-coupled logic circuit with three-state capability

Claim 1

A logic circuit comprising: a first main bipolar transistor having a base that receives a base input voltage, an emitter coupled to a first node, and a collector coupled to a second node at which an intermediate voltage signal representative of the state of the circuit is provided; a like-polarity second main bipolar transistor having a base that receives another base input voltage, an emitter coupled to the first node, and a collector coupled to a source of a first supply voltage; a main current source, coupled between the first node and a source of a second supply voltage, for providing a main supply current at the first node; a resistor coupled between the second node and the source of the first supply voltage, the intermediate signal being (1) at a first voltage level representing a first logic state when the first transistor is off and the second transistor is on so that largely none of the main supply current flows through the resistor and (2) at a second voltage level representing a second logic state when the first transistor is on and the second transistor is off so that largely all of the main supply current flows through the resistor, the second level being closer to the second supply voltage than the first level; and a like-polarity bipolar output transistor having a base coupled to the second node, an emitter coupled to an output terminal, and a collector coupled to a voltage source, the output transistor being on when the intermediate signal is at the first level or the second level so that the output terminal exhibits low impedance to further circuitry driven from the output terminal, the further circuitry preventing the voltage at the output terminal from getting any closer to the second supply voltage than a termination voltage lying between the supply voltages; characterized by switching means responsive to an output control signal when it is at a specified condition for causing current exceeding the main supply current to flow through the resisor irrespective of the conductive conditions of the main transistors, the intermediate signal thereby reaching a voltage closer to the second supply voltage than the second level so as to place the circuit in a third state, the voltage of the intermediate signal being sufficiently close to the termination voltage whenever the output control signal is at the specified condition that the output transistor turns off when the circuit is in the third state, whereby the output terminal exhibits high impedance to the further circuitry.