Abstract A circuit configuration for synchronous clock generation of at least two clock signals, includes an enable stage for receiving a clock signal and enabling the clock signal under the control of an enable signal. A branching stage for receiving the enabled clock signal from the enable stage generates at least two clock signals from the enabled clock signal. Logic and/or driver stages are each connected downstream of the branching stage for receiving a respective one of the clock signals generated by the branching stage. Each of the logic and/or driver stages has an output at which a respective output clock signal can be picked up. Amplifiers are each connected to the output of a respective one of the other stages and are associated with a respective one of the output clock signals, for detecting edges of the output clock signals. A logic array connected to the amplifiers logically links the output signals generated by the amplifiers. The logic array generates the enable signal for controlling the enable stage.
A circuit configuration for synchronous clock generation of at least two clock signals, comprising: an enable stage for receiving a clock signal and enabling the clock signal under the control of an enable signal; a branching stage for receiving the enabled clock signal from said enable stage and generating at least two clock signals from the enabled clock signal; other stages each being connected downstream of said branching stage for receiving a respective one of the clock signals generated by said branching stage, each of said other stages having an output at which a respective output clock signal can be picked up; amplifiers each being connected to the output of a respective one of said other stages and being associated with a respective one of the output clock signals, for detecting edges of the output clock signals; and a logic array connected to said amplifiers for logical linking of the output signals generated by said amplifiers, said logic array generating the enable signal for controlling said enable stage.
Claim 2
Dependent Claim
168 words
A circuit configuration for synchronous clock generation of at least two clock signals, comprising: an enable stage for receiving a clock signal and enabling the clock signal under the control of an enable signal; a branching stage for receiving the enabled clock signal from said enable stage and generating at least two clock signals from the enabled clock signal; other stages each being connected downstream of said branching stage for receiving a respective one of the clock signals generated by said branching stage, each of said other stages having an output at which a respective output clock signal can be picked up; amplifiers each being connected to the output of a respective one of said other stages and being associated with a respective one of the output clock signals, for detecting edges of the output clock signals; and a logic array connected to said amplifiers for logical linking of the output signals generated by said amplifiers, said logic array generating the enable signal for controlling said enable stage.
Claim 3
Dependent Claim
14 words
The circuit configuration according to claim 1, wherein said other stages are logic stages.
Claim 4
Dependent Claim
14 words
The circuit configuration according to claim 1, wherein said other stages are driver stages.
Claim 5
Dependent Claim
17 words
The circuit configuration according to claim 1, wherein said other stages are logic stages and driver stages.
Claim 6
Dependent Claim
24 words
The circuit configuration according to claim 1, wherein said amplifiers have an operating point located near a negative supply potential of a supply voltage.