US5468684A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit with layered superlattice material and method of fabricating same
Assignee: Olympus Corp
•
Filing: 1993-05-21
•
Granted: 1995-11-21
•
Expires: 2013-05-21
Abstract
Abstract A method of fabricating a ferroelectric or layered superlattice DRAM compatible with conventional silicon CMOS technology. A MOSFET is formed on a silicon substrate. A thick layer of BPSG followed by a thin SOG layer overlies the MOSFET. A capacitor is formed by depositing a layer of platinum, annealing, depositing an intermediate layer comprising a ferroelectric or layered superlattice material, annealing, depositing a second layer of platinum, then patterning the capacitor. Another SOG layer is deposited, contact holes to the MOSFET and capacitor are partially opened, the SOG is annealed, the contact holes are completely opened, and a Pt/Ti/PtSi wiring layer is deposited.
Inventors
- 👤 Hiroyuki Yoshimori
- 👤 Hitoshi Watanabe
- 👤 Carlos A. Paz de Araujo
- 👤 Shuzo Hiraide
- 👤 Takashi Mihara
- 👤 Larry D. McMillan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 15:16
CPC Classifications
C; C23; C23C; C23C16/00; C23C16/02; C23C16/0209; C23C16/0218; B; B05; B05D; B05D1/00; B05D1/60; B05D3/00; B05D3/04; B05D3/0493; C23C16/22; C23C16/30; C23C16/40; C23C16/44; C23C16/4412; C23C16/448; C23C16/4486; C23C16/455; C23C16/45561; C23C16/45563; C23C16/4558; C23C16/46; C23C16/48; C23C16/482; C23C16/52; C23C16/56; C23C18/00; C23C18/02; C23C18/12; C23C18/1204; C23C18/1208; C23C18/1216; C23C18/1225; C23C26/00; C23C26/02; C30; C30B; C30B25/00; C30B25/02; C30B29/00; C30B29/60; C30B29/68; C30B7/00; H; H01; H01C; H01C7/00; H01C7/10; H01C7/1013; H10; H10B; H10B12/00; H10B12/30; H10B53/00; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/682; H10D1/684; H10D1/692; H10N; H10N30/00; H10N30/01; H10N30/07; H10N30/074; H10N30/077; H05; H05K; H05K3/00; H05K3/10; H05K3/105; H10N30/80; H10N30/85; H10N30/853; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/6342; H10P14/66; H10P14/662; H10P14/668; H10P14/6681; H10P14/6684; H10P14/6686; H10P14/69; H10P14/692; H10P14/6921; H10P14/6922; H10P14/6923; H10P14/6938; H10P14/69398
Claims Analysis
Total Claims: 52
Claim 1
Independent Claim
90 words
A method of fabricating an integrated circuit, said method comprising the steps of: providing a substrate comprising silicon; forming a first electrode on said substrate; annealing said first electrode; forming an intermediate layer on said first electrode before patterning of said first electrode, said intermediate layer comprising a material selected from a group consisting of ferroelectric materials and layered superlattice materials; annealing said intermediate layer; forming a second electrode on said intermediate layer; then, subsequent to the above steps, patterning said first electrode, said intermediate layer, and said second electrode.
Claim 2
Independent Claim
90 words
A method of fabricating an integrated circuit, said method comprising the steps of: providing a substrate comprising silicon; forming a first electrode on said substrate; annealing said first electrode; forming an intermediate layer on said first electrode before patterning of said first electrode, said intermediate layer comprising a material selected from a group consisting of ferroelectric materials and layered superlattice materials; annealing said intermediate layer; forming a second electrode on said intermediate layer; then, subsequent to the above steps, patterning said first electrode, said intermediate layer, and said second electrode.
Claim 3
Dependent Claim
63 words
A method of fabricating an integrated circuit as in claim 1 wherein said step of forming said first electrode comprises depositing a layer of platinum, and said step of annealing said first electrode comprises heating to a temperature of between 750° C. and 850° C. for a period of between 15 minutes and one hour subsequent to said step of depositing said platinum.
Claim 4
Dependent Claim
57 words
A method of fabricating an integrated circuit as in claim 2 wherein said step of forming said first electrode comprises depositing a layer of titanium prior to depositing said layer of platinum, and said step of annealing said first electrode further comprises annealing said layer of titanium prior to said step of depositing said layer of platinum.
Claim 5
Dependent Claim
31 words
A method of fabricating an integrated circuit as in claim 1 wherein said step of patterning comprises etching said second electrode, then etching said first electrode, then etching said intermediate layer.
Claim 6
Dependent Claim
30 words
A method of fabricating an integrated circuit as in claim 1 wherein said step of patterning comprises etching said first electrode, etching said second electrode, then etching said intermediate layer.
Claim 7
Dependent Claim
30 words
A method of fabricating an integrated circuit as in claim 1 wherein said step of patterning comprises etching said second electrode, etching said intermediate layer, then etching said first electrode.
Claim 8
Independent Claim
86 words
A method of fabricating an integrated circuit, said method comprising the steps of: providing a substrate; forming a capacitor on said substrate, said capacitor including an intermediate layer comprising a material selected from a group consisting of ferroelectric materials and layered superlattice materials; spin coating a layer of insulator over said capacitor; treating said insulator in three or more heating steps to form a solid insulating layer over said capacitor, the temperature of each heating step being at a higher temperature than the previous heating step.
Claim 9
Independent Claim
86 words
A method of fabricating an integrated circuit, said method comprising the steps of: providing a substrate; forming a capacitor on said substrate, said capacitor including an intermediate layer comprising a material selected from a group consisting of ferroelectric materials and layered superlattice materials; spin coating a layer of insulator over said capacitor; treating said insulator in three or more heating steps to form a solid insulating layer over said capacitor, the temperature of each heating step being at a higher temperature than the previous heating step.
Claim 10
Dependent Claim
11 words
A method as in claim 7 wherein said insulator is SOG.
Claim 11
Dependent Claim
16 words
A method as in claim 7 wherein said intermediate layer comprises a ferroelectric layered superlattice material.
Claim 12
Dependent Claim
26 words
A method as in claim 7 wherein said step of treating said insulator comprises drying said insulator in a series of two or more drying steps.
Claim 13
Dependent Claim
48 words
A method as in claim 10 wherein said step of treating said insulator further comprises, subsequent to said drying steps, curing said insulator in a series of three or more curing steps, the temperature being ramped up and down in said series of three or more curing steps.
Claim 14
Dependent Claim
48 words
A method as in claim 11 wherein said step of treating said insulator further comprises, subsequent to said curing steps, baking said insulator in a series of three or more baking steps, the temperature being ramped up and down in said series of three or more baking steps.
Claim 15
Dependent Claim
24 words
A method as in claim 12 wherein the lowest temperature of said baking steps is equal to the highest temperature of said curing steps.
Claim 16
Dependent Claim
55 words
A method as in claim 13 wherein each of said drying steps is at a temperature between 75° C. and 325° C., each of said curing steps is at a temperature of between 325° C. and 475° C., and each of said baking steps is at a temperature of between 400° C. and 825° C.
Claim 17
Independent Claim
169 words
A method of fabricating an integrated circuit, said method comprising the steps of: providing a substrate; forming a transistor on said substrate, said transistor including an active area; forming a first insulating layer overlying said transistor; forming a capacitor on said first insulating layer without first providing a contact hole through said first insulating layer to said active area, said capacitor including a first electrode, an intermediate layer overlying said first electrode and comprising a material selected from a group consisting of ferroelectric materials and layered superlattice materials, and a second electrode overlying said intermediate layer; forming a second insulating layer overlying said capacitor; thereafter performing a first etch through a first mask pattern to form a contact hole to at least one of said first electrode and said second electrode; performing a second etch through a second etch pattern to form a contact hole to said active area; and forming a wiring layer contacting said active area and one of either said first electrode or said second electrode.
Claim 18
Independent Claim
169 words
A method of fabricating an integrated circuit, said method comprising the steps of: providing a substrate; forming a transistor on said substrate, said transistor including an active area; forming a first insulating layer overlying said transistor; forming a capacitor on said first insulating layer without first providing a contact hole through said first insulating layer to said active area, said capacitor including a first electrode, an intermediate layer overlying said first electrode and comprising a material selected from a group consisting of ferroelectric materials and layered superlattice materials, and a second electrode overlying said intermediate layer; forming a second insulating layer overlying said capacitor; thereafter performing a first etch through a first mask pattern to form a contact hole to at least one of said first electrode and said second electrode; performing a second etch through a second etch pattern to form a contact hole to said active area; and forming a wiring layer contacting said active area and one of either said first electrode or said second electrode.
Claim 19
Dependent Claim
42 words
A method as in claim 15 wherein said first etch etches completely down to said one at least one of said first and second electrodes and partially down to said active area, and said second etch etches down to said active area.
Claim 20
Dependent Claim
30 words
A method as in claim 15 and further including a third etch to etch the natural oxide from said contact holes prior to said step of forming said wiring layer.
Claim 21
Dependent Claim
42 words
A method as in claim 16 wherein said substrate comprises silicon and said second etch step further includes an additional etch using one or more etch materials from the group comprising: HNO 3 , HF, CH 3 COOH, and H 2 O.
Claim 22
Dependent Claim
12 words
A method as in claim 15 wherein said etches are wet etches.
Claim 23
Dependent Claim
26 words
A method as in claim 19 wherein said wet etches comprise an etch material from the group comprising: HF, NH 4 F, and CH 3 COOH.
Claim 24
Dependent Claim
37 words
A method as in claim 20 wherein said first etch and said second etch each comprises an etch with one part HF and six parts NH 4 F, and said third etch comprises HF diluted with water.
Claim 25
Dependent Claim
42 words
A method as in claim 21 wherein said substrate comprises silicon and said second etch step further includes an additional etch using one or more etch materials from the group comprising: HNO 3 , HF, CH 3 COOH, and H 2 O.
Claim 26
Dependent Claim
31 words
A method as in claim 15 wherein the contact hole size in said second mask pattern is equal to or smaller than the contact hole size of said first mask pattern.
Claim 27
Dependent Claim
25 words
A method as in claim 15 and further including an anneal step between said first etch step and said step of forming a wiring layer.
Claim 28
Dependent Claim
18 words
A method as in claim 24 wherein said anneal step is performed between said first and second etches.
Claim 29
Dependent Claim
30 words
A method as in claim 15 and further including the step of performing a first electrode anneal between said steps of forming said first electrode and forming said intermediate layer.
Claim 30
Dependent Claim
35 words
A method as in claim 15 and further including the step of performing a second insulating layer anneal between said steps of forming a second insulating layer and said step of performing a second etch.
Claim 31
Dependent Claim
59 words
A method as in claim 15 wherein said step of forming said wiring layer comprises the steps of depositing said metal wiring layer then annealing said integrated circuit at a temperature of between 350° C. and 600° C. for ten minutes or more in an atmosphere enriched in one or more gases of the group comprising nitrogen and hydrogen.
Claim 32
Independent Claim
171 words
A method of fabricating an integrated circuit, said method comprising the steps of: providing a substrate comprising silicon; forming a transistor on said substrate, said transistor including an active area; forming a first insulating layer overlying said transistor; forming a capacitor on said first insulating layer without first providing a contact hole through said first insulating layer to said active area, said capacitor including a first electrode, an intermediate layer overlying said first electrode and comprising a material selected from a group consisting of ferroelectric materials and layered superlattice materials, and a second electrode overlying said intermediate layer; thereafter forming a second insulating layer overlying said capacitor; forming contact holes to said active area and to at least one of said first electrode and said second electrode; forming a wiring layer contacting said active area and one of either said first electrode or said second electrode; and said method further including an anneal step between said step of forming a second insulating layer and said step of forming a wiring layer.
Claim 33
Independent Claim
171 words
A method of fabricating an integrated circuit, said method comprising the steps of: providing a substrate comprising silicon; forming a transistor on said substrate, said transistor including an active area; forming a first insulating layer overlying said transistor; forming a capacitor on said first insulating layer without first providing a contact hole through said first insulating layer to said active area, said capacitor including a first electrode, an intermediate layer overlying said first electrode and comprising a material selected from a group consisting of ferroelectric materials and layered superlattice materials, and a second electrode overlying said intermediate layer; thereafter forming a second insulating layer overlying said capacitor; forming contact holes to said active area and to at least one of said first electrode and said second electrode; forming a wiring layer contacting said active area and one of either said first electrode or said second electrode; and said method further including an anneal step between said step of forming a second insulating layer and said step of forming a wiring layer.
Claim 34
Dependent Claim
57 words
A method of fabricating an integrated circuit as in claim 29 wherein said step of forming said second insulating layer comprises depositing a layer of spin-on glass, and said anneal step comprises hard baking said spin-on-glass at a temperature between of between 750° C. and 850° C. for a period of between 15 minutes and one hour.
Claim 35
Dependent Claim
59 words
A method of fabricating an integrated circuit as in claim 30 wherein said step of forming contact holes comprises the steps of partially opening said contact holes in a first process, and subsequently opening said contact holes completely in a second process, and wherein said step of hard baking takes place between said first process and said second process.
Claim 36
Dependent Claim
57 words
A method of fabricating an integrated circuit as in claim 29 wherein said step of forming contact holes comprises the steps of partially opening said contact holes in a first process, and subsequently opening said contact holes completely in a second process, and wherein said anneal step takes place between said first process and said second process.
Claim 37
Independent Claim
155 words
A method of fabricating an integrated circuit, said method comprising the steps of: providing a silicon substrate; forming a transistor on said substrate, said transistor including a first active area; forming a first insulating layer overlying said transistor, said first insulating layer comprising a material from the group comprising BPSG and SOG; forming a first electrode overlying said first insulating layer without first providing a contact hole through said first insulating layer to said active area, said first electrode consisting essentially of platinum; forming an intermediate layer overlying said first electrode and comprising a material selected from a group consisting of ferroelectric materials and layered superlattice materials; forming a second electrode overlying said intermediate layer; forming a second insulating layer overlying said capacitor, said second insulating layer comprising SOG; forming a wiring layer making electrical contact with said active area and one of either said first electrode and second electrode, said wiring layer comprising platinum.
Claim 38
Independent Claim
155 words
A method of fabricating an integrated circuit, said method comprising the steps of: providing a silicon substrate; forming a transistor on said substrate, said transistor including a first active area; forming a first insulating layer overlying said transistor, said first insulating layer comprising a material from the group comprising BPSG and SOG; forming a first electrode overlying said first insulating layer without first providing a contact hole through said first insulating layer to said active area, said first electrode consisting essentially of platinum; forming an intermediate layer overlying said first electrode and comprising a material selected from a group consisting of ferroelectric materials and layered superlattice materials; forming a second electrode overlying said intermediate layer; forming a second insulating layer overlying said capacitor, said second insulating layer comprising SOG; forming a wiring layer making electrical contact with said active area and one of either said first electrode and second electrode, said wiring layer comprising platinum.
Claim 39
Dependent Claim
26 words
A method as in claim 33 wherein said first insulating layer comprises a relatively thick layer of BPSG covered by a relatively thin layer of SOG.
Claim 40
Dependent Claim
14 words
A method as in claim 33 wherein said second insulating layer comprises phosphosilicate SOG.
Claim 41
Dependent Claim
30 words
A method as in claim 33 wherein said wiring layer comprises a first wiring layer comprising platinum, a second wiring layer comprising titanium, and a third wiring layer comprising platinum.
Claim 42
Dependent Claim
14 words
A method as in claim 33 wherein said first wiring layer comprises platinum silicide.
Claim 43
Dependent Claim
49 words
A method as in claim 33 wherein said active area is formed in said silicon substrate and said first wiring layer of platinum silicide contacts said silicon substrate at said active area and said third wiring layer contacts said one of either said first electrode and said second electrode.
Claim 44
Independent Claim
173 words
A method of fabricating an integrated circuit comprising: providing a substrate comprising silicon; forming a MOS device on said substrate; forming a first insulating layer over said MOS device; forming a second device over said first insulating layer without first providing a contact hole through said first insulating layer to said MOS device, said second device comprising a material selected from a group consisting of ferroelectric materials and layered superlattice materials; forming a second insulating layer overlying said MOS device and said second device; forming a first wiring layer contact hole through said first and second insulating layers to said MOS device and a second wiring layer contact hole through said second insulating layer to said second device; forming a first wiring metal layer in at least one of said contact holes; annealing said integrated circuit to improve the electrical characteristics of said MOS device; forming a second wiring metal layer in one or more of said contact holes to connect said MOS device to said second device; and completing said integrated circuit.
Claim 45
Independent Claim
173 words
A method of fabricating an integrated circuit comprising: providing a substrate comprising silicon; forming a MOS device on said substrate; forming a first insulating layer over said MOS device; forming a second device over said first insulating layer without first providing a contact hole through said first insulating layer to said MOS device, said second device comprising a material selected from a group consisting of ferroelectric materials and layered superlattice materials; forming a second insulating layer overlying said MOS device and said second device; forming a first wiring layer contact hole through said first and second insulating layers to said MOS device and a second wiring layer contact hole through said second insulating layer to said second device; forming a first wiring metal layer in at least one of said contact holes; annealing said integrated circuit to improve the electrical characteristics of said MOS device; forming a second wiring metal layer in one or more of said contact holes to connect said MOS device to said second device; and completing said integrated circuit.
Claim 46
Dependent Claim
39 words
A method of fabricating an integrated circuit as in claim 39 wherein said step of annealing comprises heating to 350° C. or more in an atmosphere enriched in one or more of the following gases: nitrogen, hydrogen, and oxygen.
Claim 47
Dependent Claim
29 words
A method of fabricating an integrated circuit as in claim 40 wherein said step of annealing comprises annealing in an atmosphere enriched in a mixture of nitrogen and hydrogen.
Claim 48
Dependent Claim
19 words
A method of fabricating an integrated circuit as in claim 39 wherein said first wiring metal layer comprises platinum.
Claim 49
Dependent Claim
55 words
A method of fabricating an integrated circuit as in claim 42 wherein said step of forming said first metal wiring layer comprises depositing a layer of platinum on said silicon substrate, and said step of annealing further comprises causing at least of portion of said platinum and said silicon to combine to form platinum silicide.
Claim 50
Dependent Claim
21 words
A method of fabricating an integrated circuit as in claim 39 wherein said second device comprises a ferroelectric layered superlattice material.
Claim 51
Dependent Claim
21 words
A method of fabricating an integrated circuit as in claim 44 wherein said ferroelctric layered superlattice material comprises strontium bismuth tantalate.
Claim 52
Dependent Claim
40 words
A method of fabricating an integrated circuit as in claim 39 and further including the step of etching said 1st wiring metal layer between said step of forming said first metal wiring layer and forming said second metal wiring layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1998-11-20 | 1999-05-22 | 1999-11-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-11-20 | 2003-05-22 | 2003-11-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-11-20 | 2007-05-22 | 2007-11-21 | $7700.00 | Window Closed / Lapsed |