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US5467466A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for switching between a plurality of clock sources upon detection of phase alignment thereof and disabling all other clock sources

Assignee: Unisys Corp
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Filing: 1994-11-14
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Granted: 1995-11-14
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Expires: 2014-11-14
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Abstract

Abstract Systems allowing smooth, trouble-free, "transparent" switchover from a "Primary clock" to a "Secondary clock", with no loss of clock or essential pulse-width, and where the "Secondary clock" may be completely separate from, and independent of, the "Primary clock."

Inventors

  • 👤 Robert H. Carlson

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-05 03:33
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/08; H; H04; H04L; H04L7/00; H04L7/0079; H04L7/0083

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 161 words
A method for automatically bilaterally switching between a first clock-generating stage and N auxiliary clock-generating stages upon occurrance of a prescribed switchover event, this method comprising: providing N+1 like Dynamic Switchover circuits, and coupling each to a respective clock-generating stage, each Switchover circuit comprising an input Phase-compare stage, a clock control stage and a clock-internal-control stage; coupling said compare stage to receive the outputs from all clock-generating stages, and adapting it to output an enable signal E upon detection of alignment of the phase of its clock signals with those of the then-Primary clock, coupling said clock-control stage at the output of said phase compare stage and adapting it to output clock-output enable/switchover-initiating signals s-i; arranging said clock-internal-control stage to include clock buffer means, and coupling it to receive the output of all such clock-control stages while adapting it to allow output of such switchover-initiating signals s-i responsive to receipt of a prescribed disable, signal indicating occurrance of said switchover event.
Claim 2
Independent Claim 161 words
A method for automatically bilaterally switching between a first clock-generating stage and N auxiliary clock-generating stages upon occurrance of a prescribed switchover event, this method comprising: providing N+1 like Dynamic Switchover circuits, and coupling each to a respective clock-generating stage, each Switchover circuit comprising an input Phase-compare stage, a clock control stage and a clock-internal-control stage; coupling said compare stage to receive the outputs from all clock-generating stages, and adapting it to output an enable signal E upon detection of alignment of the phase of its clock signals with those of the then-Primary clock, coupling said clock-control stage at the output of said phase compare stage and adapting it to output clock-output enable/switchover-initiating signals s-i; arranging said clock-internal-control stage to include clock buffer means, and coupling it to receive the output of all such clock-control stages while adapting it to allow output of such switchover-initiating signals s-i responsive to receipt of a prescribed disable, signal indicating occurrance of said switchover event.
Claim 3
Independent Claim 191 words
A method for automatically, bilaterally switching between a first clock-generating unit and a second like, auxiliary clock-generating unit, this method comprising: providing a pair of like first and second dynamic switchover circuits, coupling each to receive the clock output C-1, C-2 from a respective unit and adapting each to pass an associated version of the respective first or second clock output to common utilization means; arranging each said switchover circuit to comprise, in combination, compare means and control means; coupling said compare means to receive both said clock outputs (C-1, C-2), along with a "switchover-enable" signal (SE), a "Primary Select" signal (PS) and a "power-up clear" signal (PUC) and adapting it to generate an "OK to switchover" signal, (OK) upon detecting suitable alignment of said clock outputs (C-1, C-2); and coupling said control means to receive said compare output (OK) along with said Primary Select, Power-up Clear signals (PS, PUC) plus a disable signal (Dis) from the companion switchover circuit, while adapting it to generate an associated switch-enable signal (SE) and a companion disable signal (Dis), these applied to, respectively, enable its own clock-output and inhibit the other, companion clock output.
Claim 4
Independent Claim 191 words
A method for automatically, bilaterally switching between a first clock-generating unit and a second like, auxiliary clock-generating unit, this method comprising: providing a pair of like first and second dynamic switchover circuits, coupling each to receive the clock output C-1, C-2 from a respective unit and adapting each to pass an associated version of the respective first or second clock output to common utilization means; arranging each said switchover circuit to comprise, in combination, compare means and control means; coupling said compare means to receive both said clock outputs (C-1, C-2), along with a "switchover-enable" signal (SE), a "Primary Select" signal (PS) and a "power-up clear" signal (PUC) and adapting it to generate an "OK to switchover" signal, (OK) upon detecting suitable alignment of said clock outputs (C-1, C-2); and coupling said control means to receive said compare output (OK) along with said Primary Select, Power-up Clear signals (PS, PUC) plus a disable signal (Dis) from the companion switchover circuit, while adapting it to generate an associated switch-enable signal (SE) and a companion disable signal (Dis), these applied to, respectively, enable its own clock-output and inhibit the other, companion clock output.
Claim 5
Independent Claim 212 words
A method for automatically, bilaterally switching between a first clock-generating unit providing output C-1 and a second like, independent auxiliary clock-generating unit providing output C-2 upon occurance of a switchover-event, this method comprising: providing a pair of like first and second dynamic switchover circuits, coupling each to receive a respective clock output C-1, C-2 and adapting each to pass an associated version of its said clock output to common utilization means; arranging each said switchover circuit to comprise, in combination, compare means, and control means; coupling said compare means to receive both said clock outputs (C-1, C-2), and to receive "switchover-enable" signals (SE), "Primary Select" signals (PS) and "power-up clear" signals (PUC); while adapting this compare means to generate an "OK to switchover" output signal, (OK) upon detecting suitable alignment of said clock outputs (C-1, C-2); coupling said control means to receive said compare means output signal (OK) along with said Primary (PS) select signals and said Power-up clear signals (PUC) plus a disable signal (Dis) from the companion switchover circuit, while adapting this control means to generate an associated switch-enable signal SE and a companion disable signal (Dis), applying said switch-enable signals (SE) to enable its own clock-output and applying said disable signals (DIS) to inhibit the other, companion clock output.
Claim 6
Independent Claim 212 words
A method for automatically, bilaterally switching between a first clock-generating unit providing output C-1 and a second like, independent auxiliary clock-generating unit providing output C-2 upon occurance of a switchover-event, this method comprising: providing a pair of like first and second dynamic switchover circuits, coupling each to receive a respective clock output C-1, C-2 and adapting each to pass an associated version of its said clock output to common utilization means; arranging each said switchover circuit to comprise, in combination, compare means, and control means; coupling said compare means to receive both said clock outputs (C-1, C-2), and to receive "switchover-enable" signals (SE), "Primary Select" signals (PS) and "power-up clear" signals (PUC); while adapting this compare means to generate an "OK to switchover" output signal, (OK) upon detecting suitable alignment of said clock outputs (C-1, C-2); coupling said control means to receive said compare means output signal (OK) along with said Primary (PS) select signals and said Power-up clear signals (PUC) plus a disable signal (Dis) from the companion switchover circuit, while adapting this control means to generate an associated switch-enable signal SE and a companion disable signal (Dis), applying said switch-enable signals (SE) to enable its own clock-output and applying said disable signals (DIS) to inhibit the other, companion clock output.
Claim 7
Dependent Claim 50 words
The method of claim 3 wherein each said control means is arranged to include a clock-internal-control stage coupled to receive the output of the other said compare means and adapted to output switchover-initiating signals (S-C) responsive to receipt of a prescribed disable signal (DS) indicating occurrance of said "switchover event."
Claim 8
Dependent Claim 15 words
The method of claim 4 wherein said clock-internal-control-stage is arranged to include buffer storage means.
Claim 9
Dependent Claim 32 words
The method of claim 4 wherein each said compare means is adapted to output a prescribed enable signal (e) upon detecting phase alignment of its clock signals with the other clock signals.

References Cited (Backward Citations)

US4490581A Cited
US4748417A Cited
US4882738A Cited
US4970405A Cited
US4853653A Cited
US5099141A Cited
US5052030A Cited
US5122677A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-11-13 1999-05-15 1999-11-14 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-11-13 2003-05-15 2003-11-14 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-11-13 2007-05-15 2007-11-14 $7700.00 Window Closed / Lapsed

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