Semiconductor device having a multilayer interconnection layer

Claim 2

A semiconductor device comprising: (a) a semiconductor substrate; (b) a conductive region substantially made of a semiconductor substance; (c) an insulating layer covering a surface of said semiconductor substrate at an area including said conductive region; (d) a contact hole formed in said insulation layer to electrically connect with said conductive region, said contact hole formed by removing a part of said insulating layer; and (e) a multilayer interconnection layer electrically connecting to said conductive region through said contact hole, said multilayer interconnection layer comprising: a conductive layer substantially made of polycrystalline silicon formed over said conductive region, said conductive layer formed along an inside wall of said contact hole and having a thickness smaller than a half length of a diameter of said contact hole, a refractory metal filling a recess of said contact hole over said conductive layer formed along the inside wall of said contact hole, a barrier metal layer formed over said refractory metal filling the recess of said contact hole, and a metal wiring layer made chiefly of aluminum formed over said barrier metal layer.

Claim 3

A semiconductor device comprising: (a) a semiconductor substrate; (b) a conductive region substantially made of a semiconductor substance; (c) an insulating layer covering a surface of said semiconductor substrate at an area including said conductive region; (d) a contact hole formed in said insulation layer to electrically connect with said conductive region, said contact hole formed by removing a part of said insulating layer; and (e) a multilayer interconnection layer electrically connecting to said conductive region through said contact hole, said multilayer interconnection layer comprising: a conductive layer substantially made of polycrystalline silicon formed over said conductive region, a barrier metal layer formed over said conductive layer, wherein said conductive layer has a thickness smaller than a half length of a diameter of said contact hole, said conductive layer and said barrier metal layer formed along an inside wall of said contact hole, a refractory metal filling a recess of said contact hole over said conductive layer and said barrier metal layer formed along the inside wall of said contact hole, and a metal wiring layer made chiefly of aluminum formed over said refractory metal filling the recess of said contact hole.

Claim 4

A semiconductor device comprising: (a) a semiconductor substrate; (b) a conductive region substantially made of a semiconductor substance; (c) an insulating layer covering a surface of said semiconductor substrate at an area including said conductive region; (d) a contact hole formed in said insulation layer to electrically connect with said conductive region, said contact hole formed by removing a part of said insulating layer; and (e) a multilayer interconnection layer electrically connecting to said conductive region through said contact hole, said multilayer interconnection layer comprising: a conductive layer substantially made of polycrystalline silicon formed over said conductive region, a barrier metal layer formed over said conductive layer, wherein said conductive layer has a thickness smaller than a half length of a diameter of said contact hole, said conductive layer and said barrier metal layer formed along an inside wall of said contact hole, a refractory metal filling a recess of said contact hole over said conductive layer and said barrier metal layer formed along the inside wall of said contact hole, and a metal wiring layer made chiefly of aluminum formed over said refractory metal filling the recess of said contact hole.

Claim 5

A semiconductor device comprising: (a) a semiconductor substrate; (b) a conductive region substantially made of a semiconductor substance; (c) an insulating layer covering a surface of said semiconductor substrate at an area including said conductive region; (d) a contact hole formed in said insulating layer to electrically connect with said conductive region, said contact hole formed by removing a part of said insulating layer; and (e) a multilayer interconnection layer formed over a top surface of said insulating layer and electrically connecting to said conductive region through said contact hole, said multilayer interconnection layer comprising: a conductive layer substantially made of polycrystalline silicon formed over said conductive region and said top surface of said insulating layer, said conductive layer having a thickness of at least a half length of a diameter of said contact hole, said thickness measured from said top surface of said insulating layer to a barrier metal layer, said conductive layer filling said contact hole, said barrier metal layer formed over said conductive layer filling said contact hole, and a metal wiring layer formed over said barrier metal layer.

Claim 6

A semiconductor device comprising: (a) a semiconductor substrate; (b) a conductive region substantially made of a semiconductor substance; (c) an insulating layer covering a surface of said semiconductor substrate at an area including said conductive region; (d) a contact hole formed in said insulating layer to electrically connect with said conductive region, said contact hole formed by removing a part of said insulating layer; and (e) a multilayer interconnection layer formed over a top surface of said insulating layer and electrically connecting to said conductive region through said contact hole, said multilayer interconnection layer comprising: a conductive layer substantially made of polycrystalline silicon formed over said conductive region and said top surface of said insulating layer, said conductive layer having a thickness of at least a half length of a diameter of said contact hole, said thickness measured from said top surface of said insulating layer to a barrier metal layer, said conductive layer filling said contact hole, said barrier metal layer formed over said conductive layer filling said contact hole, and a metal wiring layer formed over said barrier metal layer.

Claim 7

A semiconductor device comprising: (a) a semiconductor substrate; (b) a plurality of first conductive layers having impurities doped in a silicon material comprising said semiconductor substrate; (c) a wiring layer formed over a first insulating layer, said wiring layer substantially made of silicon; (d) a second insulating layer covering a surface of said semiconductor substrate at an area including said first conductive layers and said wiring layer; (e) contact holes formed in said second insulating layer to electrically connect with said first conductive layers and said wiring layer respectively, said contact holes formed by removing a part of said second insulating layer; and (f) a multilayer interconnection layer electrically connecting to at least one of said first conductive layers and said wiring layer through said contact holes, said multilayer interconnection layer comprising: a second conductive layer substantially made of a polycrystalline silicon and formed over said one of said first conductive layers and said wiring layer, said second conductive layer formed along an inside wall of each said contact hole and having a thickness smaller than a half length of a diameter of each said contact hole, a refractory metal filling a recess of each said contact hole over said second conductive layer formed along the inside wall of each said contact hole, a barrier metal layer formed over said refractory metal filling the recess of each said contact hole, and a metal wiring layer made chiefly of aluminum formed over said barrier metal layer.

Claim 8

A semiconductor device comprising: (a) a semiconductor substrate; (b) a plurality of first conductive layers having impurities doped in a silicon material comprising said semiconductor substrate; (c) a wiring layer formed over a first insulating layer, said wiring layer substantially made of silicon; (d) a second insulating layer covering a surface of said semiconductor substrate at an area including said first conductive layers and said wiring layer; (e) contact holes formed in said second insulating layer to electrically connect with said first conductive layers and said wiring layer respectively, said contact holes formed by removing a part of said second insulating layer; and (f) a multilayer interconnection layer electrically connecting to at least one of said first conductive layers and said wiring layer through said contact holes, said multilayer interconnection layer comprising: a second conductive layer substantially made of a polycrystalline silicon and formed over said one of said first conductive layers and said wiring layer, said second conductive layer formed along an inside wall of each said contact hole and having a thickness smaller than a half length of a diameter of each said contact hole, a refractory metal filling a recess of each said contact hole over said second conductive layer formed along the inside wall of each said contact hole, a barrier metal layer formed over said refractory metal filling the recess of each said contact hole, and a metal wiring layer made chiefly of aluminum formed over said barrier metal layer.

Claim 9

A semiconductor device comprising: (a) a semiconductor substrate; (b) a plurality of first conductive layers having impurities doped in a silicon material comprising said semiconductor substrate; (c) a wiring layer formed over a first insulating layer, said wiring layer substantially made of silicon; (d) a second insulating layer covering a surface of said semiconductor substrate at an area including said first conductive layers and said wiring layer; (e) contact holes formed in said second insulating layer to electrically connect with said first conductive layers and said wiring layer respectively, said contact holes formed by removing a part of said second insulating layer; and (f) a multilayer interconnection layer electrically connecting to at least one of said first conductive layers and said wiring layer through said contact holes, said multilayer interconnection layer comprising: a second conductive layer substantially made of a polycrystalline silicon and formed over said one of said first conductive layers and said wiring layer, said second conductive layer having a thickness smaller than a half length of a diameter of each said contact hole, a barrier metal layer formed over said second conductive layer, said second conductive layer and said barrier metal layer formed along an inside wall of each said contact hole, a refractory metal filling a recess of each said contact hole over said second conductive layer and said barrier metal layer formed along the inside wall of each said contact hole, and a metal wiring layer made chiefly of aluminum formed over said refractory metal filling the recess of each said contact hole.

Claim 10

A semiconductor device comprising: (a) a semiconductor substrate; (b) a plurality of first conductive layers having impurities doped in a silicon material comprising said semiconductor substrate; (c) a wiring layer formed over a first insulating layer, said wiring layer substantially made of silicon; (d) a second insulating layer covering a surface of said semiconductor substrate at an area including said first conductive layers and said wiring layer; (e) contact holes formed in said second insulating layer to electrically connect with said first conductive layers and said wiring layer respectively, said contact holes formed by removing a part of said second insulating layer; and (f) a multilayer interconnection layer electrically connecting to at least one of said first conductive layers and said wiring layer through said contact holes, said multilayer interconnection layer comprising: a second conductive layer substantially made of a polycrystalline silicon and formed over said one of said first conductive layers and said wiring layer, said second conductive layer having a thickness smaller than a half length of a diameter of each said contact hole, a barrier metal layer formed over said second conductive layer, said second conductive layer and said barrier metal layer formed along an inside wall of each said contact hole, a refractory metal filling a recess of each said contact hole over said second conductive layer and said barrier metal layer formed along the inside wall of each said contact hole, and a metal wiring layer made chiefly of aluminum formed over said refractory metal filling the recess of each said contact hole.

Claim 11

A semiconductor device comprising: (a) a semiconductor substrate; (b) a plurality of first conductive layers having impurities doped in a silicon material comprising said semiconductor substrate; (c) a wiring layer formed over a first insulating layer, said wiring layer substantially made of silicon; (d) a second insulating layer covering a surface of said semiconductor substrate at an area including said first conductive layers and said wiring layer; (e) contact holes formed in said second insulating layer to electrically connect with said first conductive layers and said wiring layer respectively, said contact holes formed by removing a part of said second insulating layer; and (f) a multilayer interconnection layer formed over a top surface of said second insulating layer and electrically connecting to at least one of said first conductive layers and said wiring layer through said contact holes, said multilayer interconnection layer comprising: a second conductive layer substantially made of a polycrystalline silicon and formed over said one of said first conductive layers, said wiring layer and said top surface of said second insulating layer, said second conductive layer having a thickness of at least a half length of a diameter of each said contact hole, said thickness measured from said top surface of said second insulating layer to a barrier metal layer, said second conductive layer filling a recess of each said contact hole, said barrier metal layer formed over said second conductive layer filling the recess of each said contact hole, and a metal wiring layer formed over said barrier metal layer.

Claim 12

A semiconductor device comprising: (a) a semiconductor substrate; (b) a plurality of first conductive layers having impurities doped in a silicon material comprising said semiconductor substrate; (c) a wiring layer formed over a first insulating layer, said wiring layer substantially made of silicon; (d) a second insulating layer covering a surface of said semiconductor substrate at an area including said first conductive layers and said wiring layer; (e) contact holes formed in said second insulating layer to electrically connect with said first conductive layers and said wiring layer respectively, said contact holes formed by removing a part of said second insulating layer; and (f) a multilayer interconnection layer formed over a top surface of said second insulating layer and electrically connecting to at least one of said first conductive layers and said wiring layer through said contact holes, said multilayer interconnection layer comprising: a second conductive layer substantially made of a polycrystalline silicon and formed over said one of said first conductive layers, said wiring layer and said top surface of said second insulating layer, said second conductive layer having a thickness of at least a half length of a diameter of each said contact hole, said thickness measured from said top surface of said second insulating layer to a barrier metal layer, said second conductive layer filling a recess of each said contact hole, said barrier metal layer formed over said second conductive layer filling the recess of each said contact hole, and a metal wiring layer formed over said barrier metal layer.

Claim 13

A semiconductor device comprising: (a) a semiconductor substrate; (b) a plurality of first conductive layers having impurities doped in a silicon material comprising said semiconductor substrate; (c) an insulating layer covering a surface of said semiconductor substrate including said first conductive layers; (d) contact holes formed in said insulating layer to electrically connect respectively with said first conductive layers, said contact holes formed by removing parts of said insulating layer; and (e) a multilayer interconnection layer electrically connecting to said first conductive layers through said contact holes, said multilayer interconnection layer comprising: a second conductive layer made substantially of a polycrystalline silicon and formed over said first conductive layers, said second conductive layer formed along an inside wall of each said contact hole and having a thickness smaller than a half length of a diameter of each said contact hole, a refractory metal filling a recess of each said contact hole over said second conductive layer formed along the inside wall of each said contact hole, a barrier metal layer formed over said refractory metal filling the recess of each said contact hole, and a metal wiring layer made chiefly of aluminum formed over said barrier metal layer.

Claim 14

A semiconductor device comprising: (a) a semiconductor substrate; (b) a plurality of first conductive layers having impurities doped in a silicon material comprising said semiconductor substrate; (c) an insulating layer covering a surface of said semiconductor substrate including said first conductive layers; (d) contact holes formed in said insulating layer to electrically connect respectively with said first conductive layers, said contact holes formed by removing parts of said insulating layer; and (e) a multilayer interconnection layer electrically connecting to said first conductive layers through said contact holes, said multilayer interconnection layer comprising: a second conductive layer made substantially of a polycrystalline silicon and formed over said first conductive layers, said second conductive layer formed along an inside wall of each said contact hole and having a thickness smaller than a half length of a diameter of each said contact hole, a refractory metal filling a recess of each said contact hole over said second conductive layer formed along the inside wall of each said contact hole, a barrier metal layer formed over said refractory metal filling the recess of each said contact hole, and a metal wiring layer made chiefly of aluminum formed over said barrier metal layer.

Claim 15

A semiconductor device comprising: (a) a semiconductor substrate; (b) a plurality of first conductive layers having impurities doped in a silicon material comprising said semiconductor substrate; (c) an insulating layer covering a surface of said semiconductor substrate including said first conductive layers; (d) contact holes formed in said insulating layer to electrically connect respectively with said conductive layers, said contact holes formed by removing parts of said insulating layer; and (e) a multilayer interconnection layer electrically connecting to said conductive layers through said contact holes, said multilayer interconnection layer comprising: a second conductive layer made substantially of a polycrystalline silicon and formed over said first conductive layers, said second conductive layer having a thickness smaller than a half length of a diameter of each said contact hole, a barrier metal layer formed over said second conductive layer, said second conductive layer and said barrier metal layer formed along an inside wall of each said contact hole, a refractory metal filling a recess of each said contact hole over said second conductive layer and said barrier metal formed along the inside wall of each said contact hole, and a metal wiring layer made chiefly of aluminum formed over said refractory metal filling the recess of each said contact hole.

Claim 16

A semiconductor device comprising: (a) a semiconductor substrate; (b) a plurality of first conductive layers having impurities doped in a silicon material comprising said semiconductor substrate; (c) an insulating layer covering a surface of said semiconductor substrate including said first conductive layers; (d) contact holes formed in said insulating layer to electrically connect respectively with said conductive layers, said contact holes formed by removing parts of said insulating layer; and (e) a multilayer interconnection layer electrically connecting to said conductive layers through said contact holes, said multilayer interconnection layer comprising: a second conductive layer made substantially of a polycrystalline silicon and formed over said first conductive layers, said second conductive layer having a thickness smaller than a half length of a diameter of each said contact hole, a barrier metal layer formed over said second conductive layer, said second conductive layer and said barrier metal layer formed along an inside wall of each said contact hole, a refractory metal filling a recess of each said contact hole over said second conductive layer and said barrier metal formed along the inside wall of each said contact hole, and a metal wiring layer made chiefly of aluminum formed over said refractory metal filling the recess of each said contact hole.

Claim 17

A semiconductor device comprising: (a) a semiconductor substrate; (b) a plurality of first conductive layers having impurities doped in a silicon material comprising said semiconductor substrate; (c) an insulating layer covering a surface of said semiconductor substrate including said first conductive layers; (d) contact holes formed in said insulating layer to electrically connect respectively with said first conductive layers, said contact holes formed by removing parts of said insulating layer; and (e) a multilayer interconnection layer formed over a top surface of said insulating layer and electrically connecting to said first conductive layers through said contact holes, said multilayer interconnection layer comprising: a second conductive layer made substantially of a polycrystalline silicon and formed over said first conductive layers and said top surface of said insulating layer, said second conductive layer having a thickness of at least a half length of a diameter of each said contact hole, said thickness measured from said top surface of said insulating layer to a barrier metal layer, said second conductive layer filling each said contact hole, said barrier metal layer formed over said second conductive layer, and a metal wiring layer formed over said barrier metal layer.

Claim 18

A semiconductor device comprising: (a) a semiconductor substrate; (b) a plurality of first conductive layers having impurities doped in a silicon material comprising said semiconductor substrate; (c) an insulating layer covering a surface of said semiconductor substrate including said first conductive layers; (d) contact holes formed in said insulating layer to electrically connect respectively with said first conductive layers, said contact holes formed by removing parts of said insulating layer; and (e) a multilayer interconnection layer formed over a top surface of said insulating layer and electrically connecting to said first conductive layers through said contact holes, said multilayer interconnection layer comprising: a second conductive layer made substantially of a polycrystalline silicon and formed over said first conductive layers and said top surface of said insulating layer, said second conductive layer having a thickness of at least a half length of a diameter of each said contact hole, said thickness measured from said top surface of said insulating layer to a barrier metal layer, said second conductive layer filling each said contact hole, said barrier metal layer formed over said second conductive layer, and a metal wiring layer formed over said barrier metal layer.

Claim 19

A semiconductor device comprising: (a) a semiconductor substrate; (b) a conductive region substantially made of a semiconductor substance; (c) an insulating layer covering a surface of said semiconductor substrate at an area including said conductive region; (d) a contact hole formed in said insulating layer to electrically connect with said conductive region, said contact hole formed by removing a part of said insulating layer; and (e) a multilayer interconnection layer electrically connecting to said conductive region through said contact hole, said multilayer interconnection layer comprising: a conductive layer substantially made of polycrystalline silicon formed over said conductive region, said conductive layer having a thickness smaller than a half length of a diameter of said contact hole, a barrier metal layer formed over said conductive layer, said conductive layer and said barrier metal layer formed along an inside wall of said contact hole, and a metal wiring layer made chiefly of aluminum formed over said barrier metal layer, said metal wiring layer filling a recess of said contact hole over said conductive layer and said barrier layer formed along the inside wall of the contact hole.

Claim 20

A semiconductor device comprising: (a) a semiconductor substrate; (b) a conductive region substantially made of a semiconductor substance; (c) an insulating layer covering a surface of said semiconductor substrate at an area including said conductive region; (d) a contact hole formed in said insulating layer to electrically connect with said conductive region, said contact hole formed by removing a part of said insulating layer; and (e) a multilayer interconnection layer electrically connecting to said conductive region through said contact hole, said multilayer interconnection layer comprising: a conductive layer substantially made of polycrystalline silicon formed over said conductive region, said conductive layer having a thickness smaller than a half length of a diameter of said contact hole, a barrier metal layer formed over said conductive layer, said conductive layer and said barrier metal layer formed along an inside wall of said contact hole, and a metal wiring layer made chiefly of aluminum formed over said barrier metal layer, said metal wiring layer filling a recess of said contact hole over said conductive layer and said barrier layer formed along the inside wall of the contact hole.

Claim 21

A semiconductor device comprising: (a) a semiconductor substrate; (b) a plurality of first conductive layers having impurities doped in a silicon material comprising said semiconductor substrate; (c) a wiring layer formed over a first insulating layer, said wiring layer substantially made of silicon; (d) a second insulating layer covering a surface of said semiconductor substrate at an area including said first conductive layers and said wiring layer; (e) contact holes formed in said second insulating layer to electrically connect with said first conductive layers and said wiring layer respectively, said contact holes formed by removing a part of said second insulating layer; and (f) a multilayer interconnection layer electrically connecting to at least one of said first conductive layers and said wiring layer through said contact holes, said multilayer interconnection layer comprising: a second conductive layer substantially made of a polycrystalline silicon and formed over said one of said first conductive layers and said wiring layer, said second conductive layer having a thickness smaller than a half length of a diameter of each said contact hole, a barrier metal layer formed over said second conductive layer, said second conductive layer and said barrier metal layer formed along an inside wall of each said contact hole, and a metal wiring layer made chiefly of aluminum formed over said barrier metal layer, said metal wiring layer filling a recess of each said contact hole over said second conductive layer and said barrier metal layer formed along the inside wall of each contact hole.

Claim 22

A semiconductor device comprising: (a) a semiconductor substrate; (b) a plurality of first conductive layers having impurities doped in a silicon material comprising said semiconductor substrate; (c) a wiring layer formed over a first insulating layer, said wiring layer substantially made of silicon; (d) a second insulating layer covering a surface of said semiconductor substrate at an area including said first conductive layers and said wiring layer; (e) contact holes formed in said second insulating layer to electrically connect with said first conductive layers and said wiring layer respectively, said contact holes formed by removing a part of said second insulating layer; and (f) a multilayer interconnection layer electrically connecting to at least one of said first conductive layers and said wiring layer through said contact holes, said multilayer interconnection layer comprising: a second conductive layer substantially made of a polycrystalline silicon and formed over said one of said first conductive layers and said wiring layer, said second conductive layer having a thickness smaller than a half length of a diameter of each said contact hole, a barrier metal layer formed over said second conductive layer, said second conductive layer and said barrier metal layer formed along an inside wall of each said contact hole, and a metal wiring layer made chiefly of aluminum formed over said barrier metal layer, said metal wiring layer filling a recess of each said contact hole over said second conductive layer and said barrier metal layer formed along the inside wall of each contact hole.

Claim 23

A semiconductor device comprising: (a) a semiconductor substrate; (b) a plurality of first conductive layers having impurities doped in a silicon material comprising said semiconductor substrate; (c) an insulating layer covering a surface of said semiconductor substrate including said first conductive layers; (d) contact holes formed in said insulating layer to electrically connect respectively with said first conductive layers, said contact holes formed by removing parts of said insulating layer; and (e) a multilayer interconnection layer electrically connecting to said first conductive layers through said contact holes, said multilayer interconnection layer comprising: a second conductive layer made substantially of a polycrystalline silicon and formed over said first conductive layers, said second conductive layer having a thickness smaller than a half length of a diameter of each said contact hole, a barrier metal layer formed over said second conductive layer, said second conductive layer and said barrier metal layer formed along an inside wall of each said contact hole, and a metal wiring layer made chiefly of aluminum formed over said barrier metal layer, said metal wiring layer filling a recess of each said contact hole over said second conductive layer and said barrier metal formed along the inside wall of each said contact hole.

Claim 24

A semiconductor device comprising: (a) a semiconductor substrate; (b) a plurality of first conductive layers having impurities doped in a silicon material comprising said semiconductor substrate; (c) an insulating layer covering a surface of said semiconductor substrate including said first conductive layers; (d) contact holes formed in said insulating layer to electrically connect respectively with said first conductive layers, said contact holes formed by removing parts of said insulating layer; and (e) a multilayer interconnection layer electrically connecting to said first conductive layers through said contact holes, said multilayer interconnection layer comprising: a second conductive layer made substantially of a polycrystalline silicon and formed over said first conductive layers, said second conductive layer having a thickness smaller than a half length of a diameter of each said contact hole, a barrier metal layer formed over said second conductive layer, said second conductive layer and said barrier metal layer formed along an inside wall of each said contact hole, and a metal wiring layer made chiefly of aluminum formed over said barrier metal layer, said metal wiring layer filling a recess of each said contact hole over said second conductive layer and said barrier metal formed along the inside wall of each said contact hole.