← Back to Patent Explorer
US5465003A Expired / Lapsed US ⏱️ 0.0 years remaining

Planarized local oxidation by trench-around technology

Assignee: United Microelectronics Corp
•
Filing: 1994-12-01
•
Granted: 1995-11-07
•
Expires: 2014-12-01
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A new planarized device isolation structure within a semiconductor substrate is described. The device isolation structure comprises narrow device isolation regions each consisting of a deep trench having a thin oxide covering its sidewalls and bottom and filled with silicon oxide, wide device isolation regions each consisting of two deep trenches flanking a shallow trench wherein each deep trench has a thin oxide covering its sidewalls and bottom and is filled with silicon oxide and wherein the shallow trench is filled with a field oxide. The top surface of the narrow and wide device isolation regions and the semiconductor substrate is planarized.

Inventors

  • 👤 Water Lur
  • 👤 Anna Su
  • 👤 Neng H. Shen

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 00:58
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/10; H10W10/17; H10P; H10P95/00; H10P95/06; H10P95/062; H10W10/01; H10W10/011; H10W10/014; H10W10/0143; H10W10/0145; H10W10/0147

Claims Analysis

Total Claims: 13
Claim 1
Independent Claim 52 words
A device isolation structure within a semiconductor substrate comprising: narrow device isolation regions each consisting of a deep trench; and wide device isolation regions each consisting of two deep trenches flanking a shallow trench; wherein the top surface of said narrow and wide device isolation regions and said semiconductor substrate is planarized.
Claim 2
Independent Claim 52 words
A device isolation structure within a semiconductor substrate comprising: narrow device isolation regions each consisting of a deep trench; and wide device isolation regions each consisting of two deep trenches flanking a shallow trench; wherein the top surface of said narrow and wide device isolation regions and said semiconductor substrate is planarized.
Claim 3
Dependent Claim 33 words
The device of claim 1 wherein a thin oxide covers the sidewalls and bottom of each of said deep trenches and wherein each of said deep trenches is filled with a silicon oxide.
Claim 4
Dependent Claim 46 words
The device of claim 1 wherein a thin oxide covers the sidewalls and bottom of each of said deep trenches and wherein each of said deep trenches is filled with a silicon oxide and wherein each of said shallow trenches is filled with a field oxide.
Claim 5
Dependent Claim 14 words
The device of claim 3 wherein said field oxide has no bird's beak structure.
Claim 6
Dependent Claim 20 words
The device of claim 1 wherein channel stop regions are formed underlying each of said deep and said shallow trenches.
Claim 7
Independent Claim 95 words
A device isolation structure within a semiconductor substrate comprising: narrow device isolation regions each consisting of a deep trench having a thin oxide covering its sidewalls and bottom and filled with silicon oxide; wide device isolation regions each consisting of two deep trenches flanking a shallow trench wherein each deep trench has a thin oxide covering its sidewalls and bottom and is filled with silicon oxide and wherein said shallow trench is filled with a field oxide; wherein the top surface of said narrow and wide device isolation regions and said semiconductor substrate is planarized.
Claim 8
Independent Claim 95 words
A device isolation structure within a semiconductor substrate comprising: narrow device isolation regions each consisting of a deep trench having a thin oxide covering its sidewalls and bottom and filled with silicon oxide; wide device isolation regions each consisting of two deep trenches flanking a shallow trench wherein each deep trench has a thin oxide covering its sidewalls and bottom and is filled with silicon oxide and wherein said shallow trench is filled with a field oxide; wherein the top surface of said narrow and wide device isolation regions and said semiconductor substrate is planarized.
Claim 9
Dependent Claim 14 words
The device of claim 6 wherein said field oxide has no bird's beak structure.
Claim 10
Dependent Claim 20 words
The device of claim 6 wherein channel stop regions are formed underlying each of said deep and said shallow trenches.
Claim 11
Independent Claim 100 words
A device isolation structure within a semiconductor substrate comprising: narrow device isolation regions each consisting of a deep trench having a thin oxide covering its sidewalls and bottom and filled with silicon oxide; wide device isolation regions each consisting of two deep trenches flanking a shallow trench wherein each deep trench has a thin oxide covering its sidewalls and bottom and is filled with silicon oxide and wherein said shallow trench is filled with a field oxide having no bird's beak structure; wherein the top surface of said narrow and wide device isolation regions and said semiconductor substrate is planarized.
Claim 12
Independent Claim 100 words
A device isolation structure within a semiconductor substrate comprising: narrow device isolation regions each consisting of a deep trench having a thin oxide covering its sidewalls and bottom and filled with silicon oxide; wide device isolation regions each consisting of two deep trenches flanking a shallow trench wherein each deep trench has a thin oxide covering its sidewalls and bottom and is filled with silicon oxide and wherein said shallow trench is filled with a field oxide having no bird's beak structure; wherein the top surface of said narrow and wide device isolation regions and said semiconductor substrate is planarized.
Claim 13
Dependent Claim 20 words
The device of claim 9 wherein channel stop regions are formed underlying each of said deep and said shallow trenches.

References Cited (Backward Citations)

US4211582A Cited
US4656497A Cited
US4868136A Cited
US4876216A Cited
US4836885A Cited
US4988639A Cited
US5108946A Cited
US5017999A Cited
US5096848A Cited
US5130268A Cited
US5350941A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-11-06 1999-05-08 1999-11-07 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-11-06 2003-05-08 2003-11-07 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-11-06 2007-05-08 2007-11-07 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag