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US5459427A Expired / Lapsed US ⏱️ 0.0 years remaining

DC level shifting circuit for analog circuits

Assignee: Motorola Solutions Inc
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Filing: 1994-05-06
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Granted: 1995-10-17
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Expires: 2014-05-06
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Abstract

Abstract A DC translation circuit (200) provides maximum dynamic range in DC level shifting that is temperature and process invariant. The DC translation circuit (200) includes a bandgap reference (202) and current mirror circuit (204) for providing a reference current, Iref. An op-amp circuit (210) receives an AC signal centered about a first DC level, and translates the first DC level into a second DC level using the reference current, a current mirror circuit (208), op-amp circuit (210) and resistor (R2).

Inventors

  • 👤 Mark J. Chambers
  • 👤 Fatima D. Da Costa Seidel
  • 👤 Jesus P. Finol
  • 👤 James B. Phillips

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-05 22:16
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/003

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 303 words
A direct current (DC) level shifting circuit for shifting a DC offset level of an input signal applied to an analog circuit, a power supply voltage being provided, the DC level shifting circuit comprising: a first transistor; a second transistor; a first resistor coupled to the first transistor's drain; a bandgap reference coupled with the first transistor's gate and drain and the second transistor's gate; a DC transmission circuit, coupled with the second transistor's drain; wherein the power supply voltage is applied to the DC transmission circuit, the bandgap reference, and the first resistor, whereby the bandgap reference creates a bandgap reference voltage across the first resistor, thus creating the reference current; a first op-amp having a non-inverting input terminal for receiving the DC offset level, an inverting input terminal coupled with the DC transmission circuit, and an output terminal coupled with the analog circuit; a second resistor coupled between the; first op-amp's output terminal and inverting input terminal; a second op-amp having an inverting input terminal coupled with the DC transmission circuit, a non-inverting input terminal coupled with the analog circuit, and an output terminal; and a third resistor coupled between the second op-amp's output terminal and the inverting input terminal; wherein the DC transmission circuit transmits the reference current to the first op-amp's inverting input terminal and to the second op-amp's inverting input terminal; whereby, when the DC offset level is applied to the first op-amp's non-inverting input terminal, the first op-amp shifts the DC offset level to an intermediate DC reference level that is applied to the analog circuit, the analog circuit passes the intermediate DC reference level to the second op-amp's non-inverting input terminal, and the second op-amp shifts the intermediate DC reference level to an output DC reference level that is available at the second op-amp's output terminal.
Claim 2
Dependent Claim 303 words
A direct current (DC) level shifting circuit for shifting a DC offset level of an input signal applied to an analog circuit, a power supply voltage being provided, the DC level shifting circuit comprising: a first transistor; a second transistor; a first resistor coupled to the first transistor's drain; a bandgap reference coupled with the first transistor's gate and drain and the second transistor's gate; a DC transmission circuit, coupled with the second transistor's drain; wherein the power supply voltage is applied to the DC transmission circuit, the bandgap reference, and the first resistor, whereby the bandgap reference creates a bandgap reference voltage across the first resistor, thus creating the reference current; a first op-amp having a non-inverting input terminal for receiving the DC offset level, an inverting input terminal coupled with the DC transmission circuit, and an output terminal coupled with the analog circuit; a second resistor coupled between the; first op-amp's output terminal and inverting input terminal; a second op-amp having an inverting input terminal coupled with the DC transmission circuit, a non-inverting input terminal coupled with the analog circuit, and an output terminal; and a third resistor coupled between the second op-amp's output terminal and the inverting input terminal; wherein the DC transmission circuit transmits the reference current to the first op-amp's inverting input terminal and to the second op-amp's inverting input terminal; whereby, when the DC offset level is applied to the first op-amp's non-inverting input terminal, the first op-amp shifts the DC offset level to an intermediate DC reference level that is applied to the analog circuit, the analog circuit passes the intermediate DC reference level to the second op-amp's non-inverting input terminal, and the second op-amp shifts the intermediate DC reference level to an output DC reference level that is available at the second op-amp's output terminal.
Claim 3
Dependent Claim 88 words
The DC level shifting circuit of claim 1, wherein the DC transmission circuit includes: a first current mirror circuit coupled with the first op-amp's inverting terminal; and a second current mirror circuit coupled with the second transistor's drain, the first current mirror circuit, and the second op-amp's inverting terminal such that the DC transmission circuit transmits the reference current to the first op-amp's inverting input terminal in a current sinking mode and transmits the reference current to the second op-amp's inverting input terminal in a current sourcing mode.
Claim 4
Dependent Claim 88 words
The DC level shifting circuit of claim 1, wherein the DC transmission circuit includes: a first current mirror circuit coupled with the second op-amp's inverting terminal; and a second current mirror circuit coupled with the second transistor's drain, the first current mirror circuit, and the second op-amp's inverting terminal such that the DC transmission circuit transmits the reference current to the first op-amp's inverting input terminal in a current sourcing mode and transmits the reference current to the second op-amp's inverting input terminal in a current sinking mode.
Claim 5
Dependent Claim 19 words
The DC level shifting circuit of claim 1, wherein the second resistor and the third resistor are matched resistors.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-10-16 1999-04-17 1999-10-17 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-10-16 2003-04-17 2003-10-17 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-10-16 2007-04-17 2007-10-17 $7700.00 Window Closed / Lapsed

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