Patent US5455794A successfully refreshed from Google Patents.
US5455794A
Expired / Lapsed
US
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Method and apparatus for controlling the output current provided by a charge pump circuit
Assignee: Intel Corp
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Filing: 1995-03-14
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Granted: 1995-10-03
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Expires: 2015-03-14
Abstract
Abstract An integrated circuit which provides an arrangement by which the source of voltage for erasing the flash EEPROM memory array is detected and, if the source is a charge pump, the current provided is held to a constant lower value while, if the source is an external high voltage source, then the current is allowed to flow freely without regulation except by the size of a field effect transistor device in the path from the source of voltage to the memory array. In this manner, the circuitry is adapted to function with either internal or external power sources without paying a performance penalty for either type of operation.
Inventors
- 👤 Jahanshir J. Javanifard
- 👤 Albert Fazio
- 👤 Robert E. Larsen
- 👤 James Brennan, Jr.
- 👤 Kerry D. Tedrow
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 12:07
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/30
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
129 words
A method for controlling the current furnished to source terminals of floating gate field effect transistors of a flash EEPROM memory array comprising the steps of: detecting whether a voltage furnished to source terminals of floating gate field effect transistors is derived from an external voltage source or from a charge pump, controlling the current furnished to the source terminals of floating gate field effect transistors to be a constat current of a limited value if the voltage furnished to source terminals of floating gate field effect transistors is derived from a charge pump, and allowing the current furnished to source terminals of floating gate field effect transistors to vary if the voltage furnished to source terminals of floating gate field effect transistors is derived from an external source.
Claim 2
Independent Claim
129 words
A method for controlling the current furnished to source terminals of floating gate field effect transistors of a flash EEPROM memory array comprising the steps of: detecting whether a voltage furnished to source terminals of floating gate field effect transistors is derived from an external voltage source or from a charge pump, controlling the current furnished to the source terminals of floating gate field effect transistors to be a constat current of a limited value if the voltage furnished to source terminals of floating gate field effect transistors is derived from a charge pump, and allowing the current furnished to source terminals of floating gate field effect transistors to vary if the voltage furnished to source terminals of floating gate field effect transistors is derived from an external source.
Claim 3
Dependent Claim
115 words
A method for controlling the current furnished to source terminals of floating gate field effect transistors of a flash EEPROM memory array as claimed in claim 1 in which the step of controlling the current furnished to the source terminals of floating gate field effect transistors to be a constant current of a limited value if the voltage furnished to source terminals of floating gate field effect transistors is derived from a charge pump comprising the steps of: providing a constant current, and mirroring the constant current to source terminals of floating gate field effect transistors if the voltage furnished to source terminals of floating gate field effect transistors is derived from a charge pump.
Claim 4
Independent Claim
162 words
A method for providing power to a plurality of floating gate field effect transistor devices during an erase operation, said floating gate field effect transistor devices having a gate terminal, a drain terminal and a source terminal, said method comprising the steps of: providing a charge pump circuit; generating, from said charge pump circuit, a positive voltage for source terminals of said floating gate field effect transistor devices during an erase operation; receiving power at a first terminal fro an external source; supplying power for siad erase operation from either said first terminal or said charge pump circuit to a second terminal; and regulating, at said second terminal, said powere to a first constant current when said power is supplied from said charge pump circuit, and not regulting current when said power is supplied from said external source, said first constant current being insufficient to bias a floating gate field effect transistor devices in a soft breakdown region during an erase operation.
Claim 5
Independent Claim
162 words
A method for providing power to a plurality of floating gate field effect transistor devices during an erase operation, said floating gate field effect transistor devices having a gate terminal, a drain terminal and a source terminal, said method comprising the steps of: providing a charge pump circuit; generating, from said charge pump circuit, a positive voltage for source terminals of said floating gate field effect transistor devices during an erase operation; receiving power at a first terminal fro an external source; supplying power for siad erase operation from either said first terminal or said charge pump circuit to a second terminal; and regulating, at said second terminal, said powere to a first constant current when said power is supplied from said charge pump circuit, and not regulting current when said power is supplied from said external source, said first constant current being insufficient to bias a floating gate field effect transistor devices in a soft breakdown region during an erase operation.
Claim 6
Dependent Claim
148 words
The method as set forth in claim 3, wherein the step of regulating said power to a first constant current when said power is supplied from said charge pump circuit, and not regulating current when said power is supplied from said external source comprises the steps of: coupling a constant current source, including a first transistor, to said second terminal; biasing said first transistor to activate said constant current source when said power is selectively supplied from said charge pump circuit; biasing said first transistor to inactivate said constant current source when said power is selectively supplied from said external source; and coupling a second transistor between said second terminal and said selective source terminals of said floating gate field effect transistor devices during an erase operation; and biasing said second transistor with said constant current source so as to regulate current to generate said first constant current.
References Cited (Backward Citations)
US5315547A
Cited
US5339297A
Cited
US5153854A
Cited
US5077691A
Cited
US5297096A
Cited
US5287317A
Cited
US5243561A
Cited
US5276646A
Cited
US5157278A
Cited
US5245572A
Cited
US5337281A
Cited
US5327384A
Cited
US5329488A
Cited
US5313429A
Cited
US5216588A
Cited
US5267218A
Cited
US5280447A
Cited
US5267196A
Cited
US5317535A
Cited
US5375094A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-10-02 | 1999-04-03 | 1999-10-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-10-02 | 2003-04-03 | 2003-10-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-10-02 | 2007-04-03 | 2007-10-03 | $7700.00 | Window Closed / Lapsed |