Apparatus for furnishing instructions in a microprocessor with a multi-stage pipeline processing unit for processing instruction phase and having a memory and at least three additional memory units

Claim 1

An apparatus for furnishing instructions in a microprocessor having a multi-stage pipeline processing unit for processing at least a "fetch instruction" phase, a "decode instruction" phase and an "execute instruction" phase, comprising a program memory; an address register being connected to said program memory and having contents pointing to an instruction to be processed in said program memory; an instruction register connected to said program memory for receiving the instruction during an instruction loading phase; an arithmetic calculation unit connected to said address register for calculating addresses; means connected to said address register for incrementing the contents of said address register; a multiplexer connected to said means for incrementing, to said arithmetic calculation unit, and to said address register for selecting a calculated address or an incremented successor address; at least one first additional memory unit connected to said address register for temporarily storing a jump instruction address upon the occurrence of a jump instruction and in the presence of a corresponding jump condition; at least one second additional memory unit connected to said program memory and associated with said first additional memory unit for storing an instruction belonging to a jump target address in said program memory; at least one address comparator connected to said address register and to said first additional memory unit for generating a match signal causing the instruction in said at least one second additional memory unit to be taken into said instruction register, if a match occurs between the jump instruction address and the contents of said first additional memory unit, and in the presence of the corresponding jump condition; and at least one third additional memory unit connected to said multiplexer for storing a jump target successor address in the program memory after calculation of the jump target address and for delivering the jump target successor address to said multiplexer, said multiplexer selecting the jump target successor address present in said at least one third additional memory unit upon generation of the match signal.

Claim 2

An apparatus for furnishing instructions in a microprocessor having a multi-stage pipeline processing unit for processing at least a "fetch instruction" phase, a "decode instruction" phase and an "execute instruction" phase, comprising a program memory; an address register being connected to said program memory and having contents pointing to an instruction to be processed in said program memory; an instruction register connected to said program memory for receiving the instruction during an instruction loading phase; an arithmetic calculation unit connected to said address register for calculating addresses; means connected to said address register for incrementing the contents of said address register; a multiplexer connected to said means for incrementing, to said arithmetic calculation unit, and to said address register for selecting a calculated address or an incremented successor address; at least one first additional memory unit connected to said address register for temporarily storing a jump instruction address upon the occurrence of a jump instruction and in the presence of a corresponding jump condition; at least one second additional memory unit connected to said program memory and associated with said first additional memory unit for storing an instruction belonging to a jump target address in said program memory; at least one address comparator connected to said address register and to said first additional memory unit for generating a match signal causing the instruction in said at least one second additional memory unit to be taken into said instruction register, if a match occurs between the jump instruction address and the contents of said first additional memory unit, and in the presence of the corresponding jump condition; and at least one third additional memory unit connected to said multiplexer for storing a jump target successor address in the program memory after calculation of the jump target address and for delivering the jump target successor address to said multiplexer, said multiplexer selecting the jump target successor address present in said at least one third additional memory unit upon generation of the match signal.

Claim 7

An apparatus for furnishing instructions in a microprocessor having a multi-stage pipeline processing unit for processing at least a "fetch instruction" phase, a "decode instruction" phase and an "execute instruction" phase, comprising: a program memory; an address register being connected to said program memory and having contents pointing to an instruction to be processed in said program memory; an instruction register connected to said program memory for receiving a loading of the instruction during an instruction loading phase; an arithmetic calculation unit connected to said address register for calculating addresses; means connected to said address register for incrementing the contents of said address register, a multiplexer connected to said arithmetic calculation unit, to said means for incrementing, and to said address register for selecting a calculated address or an incremented successor address; at least one first additional memory unit connected to said arithmetic calculation unit for temporarily storing a calculated jump target address upon the occurrence of a jump instruction; at least one second additional memory unit connected to said program memory and associated with said at least one first additional memory unit for storing the instruction belonging to the jump target address in said program memory; at least one address comparator connected to said arithmetic calculation unit and to said at least one first additional memory unit for generating a match signal causing the instruction in said at least one second additional memory unit to be taken into said instruction register if a match occurs between the calculated jump target address and the contents of said at least one first additional memory unit; and at least one third additional memory unit connected to said multiplexer for storing a jump target successor address after calculation of the jump target address and for delivering the jump target successor address to said multiplexer, said multiplexer selecting the jump target successor address present in said at least one third additional memory unit upon generation of said match signal.

Claim 8

An apparatus for furnishing instructions in a microprocessor having a multi-stage pipeline processing unit for processing at least a "fetch instruction" phase, a "decode instruction" phase and an "execute instruction" phase, comprising: a program memory; an address register being connected to said program memory and having contents pointing to an instruction to be processed in said program memory; an instruction register connected to said program memory for receiving a loading of the instruction during an instruction loading phase; an arithmetic calculation unit connected to said address register for calculating addresses; means connected to said address register for incrementing the contents of said address register, a multiplexer connected to said arithmetic calculation unit, to said means for incrementing, and to said address register for selecting a calculated address or an incremented successor address; at least one first additional memory unit connected to said arithmetic calculation unit for temporarily storing a calculated jump target address upon the occurrence of a jump instruction; at least one second additional memory unit connected to said program memory and associated with said at least one first additional memory unit for storing the instruction belonging to the jump target address in said program memory; at least one address comparator connected to said arithmetic calculation unit and to said at least one first additional memory unit for generating a match signal causing the instruction in said at least one second additional memory unit to be taken into said instruction register if a match occurs between the calculated jump target address and the contents of said at least one first additional memory unit; and at least one third additional memory unit connected to said multiplexer for storing a jump target successor address after calculation of the jump target address and for delivering the jump target successor address to said multiplexer, said multiplexer selecting the jump target successor address present in said at least one third additional memory unit upon generation of said match signal.