EP0135844A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
A data processor with a branch target instruction storage
Assignee: Hitachi Ltd
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Filing: 1984-08-31
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Granted: —
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Expires: 2004-08-31
Abstract
Abstract In order to allow fast execution of branch instructions even with the possibility of branching to different target instructions from the same branch instruction, a target instruction storage (102) provides the target instruction in response to the branch instruction address and address data associated with a target instruction address.
Inventors
- 👤 Shonai Tooru
- 👤 Torii Shunichi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 18:46
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3804
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
224 words
A digital processor, comprising: a main storage (12); instruction means (15) for holding instructions to be executed; means (10) connected to said main storage (12) and sequentially fetching instructions into said instruction means (15); decode means (30) connected to said instruction means (15) for detecting whether or not the instruction held thereby is a branch instruction; instruction address means (804,806,802) responsive to the fetching of an instruction into said instruction means (15) for generating an instruction address of said instruction; address data means (17,20) responsive to the branch instruction held in said instruction means (15) for generating address data related to the address of a target instruction for the branch instruction held in said instruction means (15); storage means (102) for storing plural sets of data, each including a branch instruction address, a target instruction and address data related to that target instruction; read means responsive to said instruction address means (804,806,802) and said address data means (17,20) for reading from said storage means (15) a target instruction induded in one of said sets of data which also includes said branch instruction address given by said instruction address means (804,806,802) and said address data given by said address data means (17,20); and means connected to said storage means (15) for supplying the read out target instruction from said storage means to said instruction means.
Claim 2
Dependent Claim
224 words
A digital processor, comprising: a main storage (12); instruction means (15) for holding instructions to be executed; means (10) connected to said main storage (12) and sequentially fetching instructions into said instruction means (15); decode means (30) connected to said instruction means (15) for detecting whether or not the instruction held thereby is a branch instruction; instruction address means (804,806,802) responsive to the fetching of an instruction into said instruction means (15) for generating an instruction address of said instruction; address data means (17,20) responsive to the branch instruction held in said instruction means (15) for generating address data related to the address of a target instruction for the branch instruction held in said instruction means (15); storage means (102) for storing plural sets of data, each including a branch instruction address, a target instruction and address data related to that target instruction; read means responsive to said instruction address means (804,806,802) and said address data means (17,20) for reading from said storage means (15) a target instruction induded in one of said sets of data which also includes said branch instruction address given by said instruction address means (804,806,802) and said address data given by said address data means (17,20); and means connected to said storage means (15) for supplying the read out target instruction from said storage means to said instruction means.
Claim 3
Dependent Claim
61 words
A digital processor according to claim 1, wherein said address data means (17,20) includes: register means (17), including plural general registers, responsive to a register designating field within said branch instruction held in said instruction means for selectively providing as said address data at least one value contained in at least one of said general registers designated by the branch instruction.
Claim 4
Dependent Claim
64 words
A digital processor according to claim 2, further comprising means for calculating the target instruction address of a target instruction for the branch instruction held in said instruction means (15) based on said one value obtained from said general registers (17) and means for applying said target instruction address to said main storage (12) to fetch said target instruction from said main storage (12).
Claim 5
Dependent Claim
111 words
A digital processor according to claim 1, wherein said address data means includes: register means, including plural general registers (17), responsive to plural register designating fields within said branch instruction for selectively providing, as said address data, plural values each contained in a respective one of said general registers (17) as designated by the branch instruction held in said instruction means (15); said digital processor further comprising means (20) for adding said plural values and a further field of the branch instruction to obtain a target instruction address and means for applying said target instruction address to said main storage (12) to fetch the target instruction from said main storage (12).
Claim 6
Dependent Claim
53 words
A digital processor according to claim 1, wherein said address data means (17,20) includes means responsive to the branch instruction held in said instruction means (15) for generating and providing the target instruction address of a target instruction for the branch instruction held in said instruction means (15) as said related address data.
Claim 7
Dependent Claim
33 words
A digital processor according to claim 1, wherein said address data means (17,20) includes means for providing at least part of the branch instruction held in said instruction means as said address data.
Claim 8
Dependent Claim
23 words
A digital processor according to claim 6, wherein said part of said branch instruction forming said address data is a register designating field.
Claim 9
Dependent Claim
22 words
A digital processor of claim 6, wherein said part of said branch instruction forming said address data is a displacement designating field.
Claim 10
Dependent Claim
173 words
A digital processor according to claim 1, further comprising: first means for detecting whether or not the target instruction for the branch instruction held in said instruction means (15) is already stored in said storage means (102) based on the instruction address generated by said instruction address means (804,806,802) and the address data provided by said address data means; access means responsive to the branch instruction held in said instruction means for accessing said main storage to fetch the target instruction from said main storage; second means responsive to the branch instruction held in said instruction means for detecting whether or not the branch operation required by said branch instruction is to be allowed based upon the branch instruction; write means (412) for writing a set of said target instructions fetched from said main storage (12) along with said branch instruction address and the address data relating thereto into said storage means (102), in response to a negative detection result from said first means and a positive detection result from said second means.
Claim 11
Dependent Claim
81 words
A digital processor of claim 1, further comprising: first means responsive to the branch instruction held in said instruction means (15) for detecting whether or not the branch operation required by said branch instruction is to be allowed based upon the branch instruction; and second means responsive to a negative detection result by said first means for invalidating a set of data including the target instruction for the branch instruction among the sets of data stored in said storage means (102).
Claim 12
Dependent Claim
28 words
A digital processor according to claim 1, wherein said storage means (102) comprises means for storing a branch instruction as part of each set of data stored therein.
References Cited (Backward Citations)
No citation records indexed.
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