US4835679A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Microprogram control system
Assignee: Hitachi Ltd
•
Filing: 1986-01-14
•
Granted: 1989-05-30
•
Expires: 2006-01-14
Abstract
Abstract Micro instructions having a predetermined relationship with respect to each other are modified so that an original micro instruction and address assigned thereto can be restored by combining one or more modified micro instructions and address assigned thereto. A microprogram memory stores the micro instructions in such a modified form and at the modified address. When an original address is designated, one or more term lines are activated in a decoder of the microprogram memory, and modified micro instructions corresponding to the activated term lines are read-out from a memory array of the microprogram memory. The read modified micro instructions are logically combined to restore the original micro instruction. Thereby, the number of micro instructions to be actually stored in the microprogram memory can be reduced.
Inventors
- 👤 Hiroyuki Kida
- 👤 Hideo Maejima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 03:07
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/26; G06F9/261
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
140 words
A microprogram memory arrangement for compressing microinstructions used in a microprogram control system in which the execution of a macro instruction stored in a main memory is effected by successively executing a plurality of micro instructions associated therewith, comprising: memory means for storing micro instructions of a micro program to be executed, said micro instructions being stored in a modified form on the basis of common bit patterns contained within the micro instructions; decoding means for decoding the addresses of a micro program and activating at least one micro instruction address line which is coupled to said memory means in accordance with the address applied thereto; and means for selectively combining said modified micro instructions in accordance with the activation of said micro instruction address lines by said decoding means to thereby produce a micro instruction in a restored form.
Claim 2
Dependent Claim
140 words
A microprogram memory arrangement for compressing microinstructions used in a microprogram control system in which the execution of a macro instruction stored in a main memory is effected by successively executing a plurality of micro instructions associated therewith, comprising: memory means for storing micro instructions of a micro program to be executed, said micro instructions being stored in a modified form on the basis of common bit patterns contained within the micro instructions; decoding means for decoding the addresses of a micro program and activating at least one micro instruction address line which is coupled to said memory means in accordance with the address applied thereto; and means for selectively combining said modified micro instructions in accordance with the activation of said micro instruction address lines by said decoding means to thereby produce a micro instruction in a restored form.
Claim 3
Dependent Claim
40 words
A micro program memory arrangement according to claim 1, wherein the address of an entry micro instruction of a set of micro instructions associated with a macro instruction is directly designated by the macro instruction read out from main memory.
Claim 4
Dependent Claim
56 words
A micro program memory arrangement according to claim 2, wherein said decoding means includes means for decoding a macro instruction read from said main memory so as to activate at least one micro instruction address selecting line and means for decoding a micro instruction for activating at least one of said micro instruction address selecting lines.
Claim 5
Dependent Claim
53 words
A micro program memory arrangement according to claim 1, wherein a primary micro instruction including a bit pattern of a common field causes a particular micro instruction address line, wired in accordance with said bit pattern of said common field to become activated in response to the address of an original micro instruction.
Claim 6
Dependent Claim
88 words
A micro program memory arrangement according to claim 1, wherein first micro instructions including bit patterns in a specific field of said micro instructions are formed by logically combining bit patterns in specific fields of other micro instructions, said first micro instruction being assigned memory addresses, wherein bit patterns of said assigned memory addresses of said first micro instructions can be restored by logically combining bit patterns of memory addresses of the other micro instructions, and wherein said decoding means is wired in accordance with said assigned addresses.
References Cited (Backward Citations)
US4251862A
Cited
US4348736A
Cited
US4325121A
Cited
US4394736A
Cited
US4370729A
Cited
US4467415A
Cited
US4402043A
Cited
US4468735A
Cited
US4422144A
Cited
US4509114A
Cited
US4504904A
Cited
US4566075A
Cited
US4546273A
Cited
JPS6116332A
Cited
JPS6188336A
Cited
JPS61134838A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-05-29 | 1992-11-28 | 1993-05-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-05-29 | 1996-11-28 | 1997-05-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-05-29 | 2000-11-28 | 2001-05-30 | $7700.00 | Window Closed / Lapsed |