Patent US2532103A successfully refreshed from Google Patents.
Patent US5450546A successfully refreshed from Google Patents.
US5450546A
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US
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Intelligent hardware for automatically controlling buffer memory storage space in a disk drive
Assignee: RPX Corp
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Filing: 1992-01-31
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Granted: 1995-09-12
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Expires: 2012-01-31
Abstract
Abstract An integrated disk controller integrated circuit in a disk drive includes the buffer room logic hardware of this invention within a buffer control circuit. The buffer room logic hardware monitors the status of a buffer memory as data are written into and read from the buffer memory in data transfers between a disk and another device, typically a computer. When the buffer memory is either full or empty, the buffer room logic hardware automatically generates signals that control subsequent data transfer to or from the buffer memory. Therefore, the buffer room logic hardware prevents buffer overruns and buffer underruns without intervention or other action by a microprocessor. When the buffer memory is empty, data transfer is either terminated or suspended until data become available in the buffer memory. When the buffer memory is full, the buffer room logic hardware either generates a signal that terminates the data transfer or generates a signal that suspends further data transfer until space becomes available in the buffer memory. In one embodiment, the buffer room logic hardware does not permit resumption of data transfer until a predetermined threshold value of space is available in the buffer memory.
Inventors
- 👤 Chahe H. Krakirian
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 10:54
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/06; G06F3/0601; G11; G11B; G11B20/00; G11B20/10; G06F3/0668; G06F3/0671; G06F3/0673; G11B20/10527; G11B2020/1062; G11B2020/10814
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
362 words
An integrated disk drive controller comprising: a disk control circuit having an internal data bus and a sector-ok line; a host interface circuit having: a first-in-first-out memory circuit hereinafter referred to as said FIFO; an internal data bus coupled to said FIFO; a buffer control circuit connected to said disk controller internal data bus, to said sector-ok line, and to said host interface circuit internal data bus wherein said buffer control circuit further comprises a buffer room logic circuit comprising: a plurality of control registers; a disk counter connected to at least one register in said plurality of control registers, and having a disk counter output line; wherein said disk counter generates a signal on said disk counter output line upon said disk counter counting transfer of a block of data from a buffer memory to said disk control circuit; a host counter connected to at least one register in said plurality of control registers, and having a host counter output line; wherein said host counter generates a signal on said host counter output line upon said host counter counting transfer of a block of data over said host interface circuit internal data bus; and a block counter connected to at least one register in said plurality of registers, and coupled to said disk counter output line, to said host counter output line, and to said sector-ok line, and said block counter having a minimum value and a maximum value; wherein in a read operation, (i) a signal is generated on said sector-ok line by said disk control circuit upon a block of data being transferred to said buffer memory, and said block counter counts in a first direction in response to said signal on said sector-ok line; and (ii) in response to a signal on said host counter output line, said block counter counts in a second direction that is opposite to said first direction; and in a write operation, (i) in response to a signal on said host counter output line, said block counter counts in said second direction; and (ii) in response to a signal on said disk counter output line, said block counter counts in said first direction.
Claim 2
Dependent Claim
362 words
An integrated disk drive controller comprising: a disk control circuit having an internal data bus and a sector-ok line; a host interface circuit having: a first-in-first-out memory circuit hereinafter referred to as said FIFO; an internal data bus coupled to said FIFO; a buffer control circuit connected to said disk controller internal data bus, to said sector-ok line, and to said host interface circuit internal data bus wherein said buffer control circuit further comprises a buffer room logic circuit comprising: a plurality of control registers; a disk counter connected to at least one register in said plurality of control registers, and having a disk counter output line; wherein said disk counter generates a signal on said disk counter output line upon said disk counter counting transfer of a block of data from a buffer memory to said disk control circuit; a host counter connected to at least one register in said plurality of control registers, and having a host counter output line; wherein said host counter generates a signal on said host counter output line upon said host counter counting transfer of a block of data over said host interface circuit internal data bus; and a block counter connected to at least one register in said plurality of registers, and coupled to said disk counter output line, to said host counter output line, and to said sector-ok line, and said block counter having a minimum value and a maximum value; wherein in a read operation, (i) a signal is generated on said sector-ok line by said disk control circuit upon a block of data being transferred to said buffer memory, and said block counter counts in a first direction in response to said signal on said sector-ok line; and (ii) in response to a signal on said host counter output line, said block counter counts in a second direction that is opposite to said first direction; and in a write operation, (i) in response to a signal on said host counter output line, said block counter counts in said second direction; and (ii) in response to a signal on said disk counter output line, said block counter counts in said first direction.
Claim 3
Dependent Claim
18 words
The integrated disk drive controller of claim 1 wherein said disk counter further comprises a programmable disk counter.
Claim 4
Dependent Claim
30 words
The integrated disk drive controller of claim 2 further comprising: a maximum count register having an output bus connected to a set of input terminals of said programmable disk counter.
Claim 5
Dependent Claim
33 words
The integrated disk drive controller of claim 3 wherein upon initialization of said integrated disk controller, a number of bytes in a block minus one byte is loaded in said maximum count register.
Claim 6
Dependent Claim
49 words
The integrated disk drive controller of claim 3 wherein said programmable disk counter further comprises a multiplexer having a set of input terminals connected to said maximum count register output bus wherein said set of input terminals of said programmable disk counter are said set of multiplexer input terminals.
Claim 7
Dependent Claim
18 words
The integrated disk drive controller of claim 1 wherein said host counter further comprises a programmable host counter.
Claim 8
Dependent Claim
30 words
The integrated disk drive controller of claim 6 further comprising: a maximum count register having an output bus connected to a set of input terminals of said programmable host counter.
Claim 9
Dependent Claim
33 words
The integrated disk drive controller of claim 7 wherein upon initialization of said integrated disk controller, a number of bytes in a block minus one byte is loaded in said maximum count register.
Claim 10
Dependent Claim
49 words
The integrated disk drive controller of claim 7 wherein said programmable host counter further comprises a multiplexer having a set of input terminals connected to said maximum count register output bus wherein said set of input terminals of said programmable host counter are said set of multiplexer input terminals.
Claim 11
Dependent Claim
18 words
The integrated disk drive controller of claim 1 wherein said block counter further comprises a programmable block counter.
Claim 12
Dependent Claim
31 words
The integrated disk drive controller of claim 10 further comprising: a maximum block count register having an output bus connected to a set of input terminals of said programmable block counter.
Claim 13
Dependent Claim
34 words
The integrated disk drive controller of claim 11 wherein upon initialization of said programmable block counter a number of blocks in said memory minus one block is loaded in said maximum block count register.
Claim 14
Dependent Claim
50 words
The integrated disk drive controller of claim 12 wherein said programmable block counter further comprises a multiplexer having a set of input terminals connected to said maximum block count register output bus wherein said set of input terminals of said programmable block counter are said set of multiplexer input terminals.
Claim 15
Dependent Claim
24 words
The integrated disk drive controller of claim 13 wherein said multiplexer further comprises a second set of input terminals connected to a reference voltage.
Claim 16
Dependent Claim
84 words
The integrated drive disk controller of claim 1 wherein in said write operation, said maximum value is selected to prevent a buffer memory underrun and said minimum value is selected to prevent a buffer memory overrun, and further wherein upon said block counter reaching said maximum value, a first output signal is generated to stop data transfer from said buffer memory, and upon said block counter reaching said minimum value, a second output signal is generated to stop data transfer to said buffer memory.
Claim 17
Dependent Claim
84 words
The integrated drive disk controller of claim 1 wherein in said read operation, said minimum value is selected to prevent a buffer memory underrun and said maximum value is selected to prevent a buffer memory overrun, and further wherein upon said block counter reaching said maximum value, a first output signal is generated to stop data transfer to said buffer memory, and upon said block counter reaching said minimum value, a second output signal is generated to stop data transfer from said buffer memory.
Claim 18
Dependent Claim
23 words
The integrated drive disk controller of claim 1 wherein said first direction in which said block counter counts is towards said maximum value.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-09-11 | 1999-03-13 | 1999-09-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-11 | 2003-03-13 | 2003-09-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-11 | 2007-03-13 | 2007-09-12 | $7700.00 | Window Closed / Lapsed |