Method and structure for providing error correction code for each byte on SIMM'S

Claim 2

A SIMM memory adapted to be added as add-on memory to a computer system, which system writes eight-bit bytes of data and said SIMM provides error correction for said data; and wherein said SIMM is configured to operate at a given speed for read and write operations, comprising: logic to generate at least four check bits from the eight bits of each data byte written; DRAM chips to store said generated four check bits with each data byte in said DRAM chips without introducing a wait state; logic to read each data byte and associated check bits from the DRAM and generate new check bits and compare the newly-generated check bits with the stored check bits to correct and output all single-bit errors and detect some multi-bit errors in the read data, said DRAM chips being selected to operate at a speed of at least about 10 nanoseconds faster than the speed of operation of the SIMM; and said DRAM chip including logic to provide a late write function to the DRAM.

Claim 3

The invention as defined in claim 1, further characterized by delay logic to delay the writing of data to the DRAM chips during the write operation until the check bits are generated.

Claim 4

The invention as defined in claim 2, wherein said delay logic includes a delay block and a latch.

Claim 5

The invention as defined in claim 3 wherein said latch is configured to latch valid data until it has been written to the DRAM.

Claim 6

The invention as defined in claim 4 wherein said delay logic includes logic to permit writing data during a refresh cycle.

Claim 7

The invention as defined in claim 1 wherein said logic to read the data from the DRAM chips generates new check bits, and correct the single bit error and is configured to output the corrected data within less than 10 ns.

Claim 8

A computer system comprising: a CPU and a bus having a SIMM memory added as add-on memory to said computer system, said computer system configured to write eight bit bytes of data, said SIMM including error correction for said data; said SIMM being configured to operate at a given speed for read and write operations, said SIMM including: logic to generate at least four check bits from the eight bits of each data byte written; DRAM chips to store said generated four check bits with each data byte in said SIMM without introducing a wait state; logic to read each data byte and associated check bits from the DRAM and generate new check bits and compare the newly-generated check bits with the stored check bits to correct and output all single-bit errors and detect some multi-bit errors in the read data and supply said corrected data to the system bus, said DRAM chips being selected to operate at a speed of at least about 10 nanoseconds faster than the speed of operation of the SIMM; and said DRAM chip including logic to provide a late write function to the DRAM.

Claim 9

A computer system comprising: a CPU and a bus having a SIMM memory added as add-on memory to said computer system, said computer system configured to write eight bit bytes of data, said SIMM including error correction for said data; said SIMM being configured to operate at a given speed for read and write operations, said SIMM including: logic to generate at least four check bits from the eight bits of each data byte written; DRAM chips to store said generated four check bits with each data byte in said SIMM without introducing a wait state; logic to read each data byte and associated check bits from the DRAM and generate new check bits and compare the newly-generated check bits with the stored check bits to correct and output all single-bit errors and detect some multi-bit errors in the read data and supply said corrected data to the system bus, said DRAM chips being selected to operate at a speed of at least about 10 nanoseconds faster than the speed of operation of the SIMM; and said DRAM chip including logic to provide a late write function to the DRAM.

Claim 10

The invention as defined in claim 7, further characterized by delay logic to delay the writing of data to the DRAM chips during the write operation until the check bits are generated.

Claim 11

The invention as defined in claim 8, wherein said delay logic includes a delay block and a latch.

Claim 12

The invention as defined in claim 9 wherein said latch is configured to latch valid data until it has been written to the DRAM.

Claim 13

The invention as defined in claim 10 wherein said delay logic includes logic to permit writing data during a refresh cycle.

Claim 14

The invention as defined in claim 7 wherein said logic to read the data from the DRAM chips generates new check bits, and correct the single bit error and is configured to output the corrected data within less than 10 ns.

Claim 17

The invention as defined in claim 13, further characterized by latching the data during said generation of said check bits.

Claim 18

The invention as defined in claim 13 further characterized by preventing a write operation during refresh.