Dram on-chip error correction/detection

Claim 2

Apparatus usable for detection of errors in a memory system of a computer, the computer including a central processing unit and a data bus connecting the central processing unit to the memory system, the data bus having a width equal to a first number of bits, the apparatus comprising: a random access memory device in the memory system, the memory device for storing one or more rows of bits; and error detection means for receiving a second number of data bits and third number of error correction bits from said memory device where the second and the third number of bits are from accessing an entire row from one of the rows of bits from the memory device and providing a first signal when an error is detected in said second number of bits where the second number of bits is detected in one detection cycle, said second number of bits being greater than said first number of bits, such that the number of data bits on which error detection is performed is greater than the width of said data bus.

Claim 3

Apparatus, as claimed in claim 1, wherein said first means includes means for correcting at least a first erroneous bit among said second number of bits.

Claim 4

Apparatus, as claimed in claim 1, wherein said memory device is a static column mode memory device.

Claim 5

Apparatus, as claimed in claim 1, wherein said memory device is a fast page mode memory device.

Claim 6

Apparatus, as claimed in claim 1, wherein said second number is at least 512.

Claim 7

Apparatus, as claimed in claim 1, wherein said second number is at least 2048.

Claim 8

Apparatus, as claimed in claim 1, wherein said third number is at least 13.

Claim 9

Apparatus usable for detection of errors in a memory system of a computer, the apparatus comprising: a row and column organized dynamic random access memory device for storing bits, said memory device formed on a single integrated circuit chip, said memory device including means for accessing the contents of an entire row of bits from said memory; and error correction circuitry for receiving data from the entire row of bits from said memory array and for detecting at least a first of any error in said received bits in one detection cycle, said circuitry being substantially all formed on said chip.

Claim 10

Apparatus usable for detection of errors in a memory system of a computer, the apparatus comprising: a row and column organized dynamic random access memory device for storing bits, said memory device formed on a single integrated circuit chip, said memory device including means for accessing the contents of an entire row of bits from said memory; and error correction circuitry for receiving data from the entire row of bits from said memory array and for detecting at least a first of any error in said received bits in one detection cycle, said circuitry being substantially all formed on said chip.

Claim 11

Apparatus, as claimed in claim 8, further comprising error correction circuitry for correcting at least a first erroneous bit, said correction circuitry being formed on said chip.

Claim 12

Apparatus usable for detection of errors in a memory system of a computer, the apparatus comprising: a dynamic random access memory array for storing bits at memory locations addressable by a row address and a column address, wherein a first number of bits is accessible by changing said column address while said row address remains constant, the first number of bits is equal to the number of bits in all memory locations addressed by all column addresses and by a single row address; and error detection means for receiving a first group of data bits, the number of bits in said first group being equal to said first number of bits, detecting at least a first of any error in said first group where the whole first group is detected in one detection cycle and providing a signal when an error is detected, such that a single error detection operation is performed on an entire row of said memory.

Claim 13

Apparatus usable for detection of errors in a memory system of a computer, the apparatus comprising: a dynamic random access memory array for storing bits at memory locations addressable by a row address and a column address, wherein a first number of bits is accessible by changing said column address while said row address remains constant, the first number of bits is equal to the number of bits in all memory locations addressed by all column addresses and by a single row address; and error detection means for receiving a first group of data bits, the number of bits in said first group being equal to said first number of bits, detecting at least a first of any error in said first group where the whole first group is detected in one detection cycle and providing a signal when an error is detected, such that a single error detection operation is performed on an entire row of said memory.

Claim 14

Apparatus, as claimed in claim 10, wherein said memory array and said error detection means are formed on a single integrated circuit chip.

Claim 17

A method, as claimed in claim 12, further comprising refreshing a row of said memory addressed by said first row address following said step of receiving.

Claim 18

A method, as claimed in claim 12, further comprising: asserting a first column address and a column address strobe; and reading data from at least a memory location addressed by said first row address and said first column address.

Claim 19

A method, as claimed in claim 12, further comprising: asserting a first column address and a column address strobe; and writing data to memory at a memory location addressed by said first row address and said first column address.

Claim 20

A method, as claimed in claim 12, further comprising correcting at least a first erroneous bit in said received bits and writing at least said corrected bit to said memory.

Claim 21

A method, as claimed in claim 12, further comprising: asserting at least a first column address; receiving at least a second set of said first number of bits in said error detection device; and providing a signal when an error is detected in at least a first bit among said second set of received bits when the second set of received bits is detected in one detection cycle, following said step of asserting at least a first column address.

Claim 24

A computer with apparatus usable for the detection of errors in the memory of the computer, the computer comprising: a central processing unit; a system bus having a data bus with a first number of bits, the system bus being connected to the central processing unit; a memory controller having address information and control signals connected to the system bus; a memory connected to the memory controller and receiving address information and control signals from the memory controller, the memory having one or more rows of bits, each row of the memory storing a second number of data bits and for storing a third number of error correction bits for the second number of data bits such that the second number of data bits is larger than the first number of bits; an error correction code checking and generating circuit connected to the system bus and to the memory, the circuit serving as means for receiving a second number of data bits and a third number of error correction bits from one row of the memory where the second and the third number of bits are accessed in one accessing cycle, for detecting at least a first of any error on the received second number of data bits using the third number of error correction bits in one detection cycle, and for providing an error signal when at least a first error is detected by the circuit.

Claim 25

A computer with apparatus usable for the detection of errors in the memory of the computer, the computer comprising: a central processing unit; a system bus having a data bus with a first number of bits, the system bus being connected to the central processing unit; a memory controller having address information and control signals connected to the system bus; a memory connected to the memory controller and receiving address information and control signals from the memory controller, the memory having one or more rows of bits, each row of the memory storing a second number of data bits and for storing a third number of error correction bits for the second number of data bits such that the second number of data bits is larger than the first number of bits; an error correction code checking and generating circuit connected to the system bus and to the memory, the circuit serving as means for receiving a second number of data bits and a third number of error correction bits from one row of the memory where the second and the third number of bits are accessed in one accessing cycle, for detecting at least a first of any error on the received second number of data bits using the third number of error correction bits in one detection cycle, and for providing an error signal when at least a first error is detected by the circuit.