US4903268A
Expired / Lapsed
US
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Semiconductor memory device having on-chip error check and correction functions
Assignee: Mitsubishi Electric Corp
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Filing: 1988-02-29
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Granted: 1990-02-20
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Expires: 2008-02-29
Abstract
Abstract A semiconductor memory comprises a data bit memory cell array (3), a check bit memory cell array (4), and an address decoder (19) which includes a switching circuit (20) for selectively accessing data from either the memory cell array (3) or (4). Decoding signals d l to d m are used for reading out data latched by a column address strobe (CAS) signal. The decoding signals are applied to either the memory cell array (3) or (4) through a group of switching elements selectively rendered conductive by complementary signals φ and φ. The logical values of the signals φ and φ change responsive to a change in the CAS signal state.
Inventors
- 👤 Hideto Hidaka
- 👤 Kazuyasu Fujishima
- 👤 Masaki Kumanoya
- 👤 Hideshi Miyatake
- 👤 Katsumi Dosaka
- 👤 Tsutomu Yoshihara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 20:56
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/2215; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1076
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
255 words
A semiconductor memory device having on-chip error checking and correcting functions comprising: a plurality of memory cell arrays, said arrays including a data bit memory cell array for storing data words of m bits each and a check bit memory cell array for storing data including error correction codes having k check bits each; error checking and correcting means including (a) error code generation means for receiving input data words and, in response, generating said error correction codes, (b) error code writing means for storing said error codes in said check bit memory cell array, and (c) data correction means for reading said data words stored in said data bit memory cell array and said error codes stored in said check bit array and, in response thereto, supplying a corrected data word output; clock input means for receiving a switching control signal; means for disabling said on-chip error checking and correcting means in response to an external test mode enable control signal (TE); data writing means for writing data into said memory cell arrays; and data reading means for supplying data words from said data correction means and from said check bit memory cell array, said data reading means including a single data output terminal and switching mans responsive to said switching control signal for alternatingly accessing said check bit memory cell array and said data bit memory cell array through said error checking and correction means for successively outputting check bits and data bits from said single data output terminal in an interleaved manner.
Claim 2
Dependent Claim
255 words
A semiconductor memory device having on-chip error checking and correcting functions comprising: a plurality of memory cell arrays, said arrays including a data bit memory cell array for storing data words of m bits each and a check bit memory cell array for storing data including error correction codes having k check bits each; error checking and correcting means including (a) error code generation means for receiving input data words and, in response, generating said error correction codes, (b) error code writing means for storing said error codes in said check bit memory cell array, and (c) data correction means for reading said data words stored in said data bit memory cell array and said error codes stored in said check bit array and, in response thereto, supplying a corrected data word output; clock input means for receiving a switching control signal; means for disabling said on-chip error checking and correcting means in response to an external test mode enable control signal (TE); data writing means for writing data into said memory cell arrays; and data reading means for supplying data words from said data correction means and from said check bit memory cell array, said data reading means including a single data output terminal and switching mans responsive to said switching control signal for alternatingly accessing said check bit memory cell array and said data bit memory cell array through said error checking and correction means for successively outputting check bits and data bits from said single data output terminal in an interleaved manner.
Claim 3
Dependent Claim
46 words
A semiconductor memory device in accordance with claim 1, wherein said switching means responsive to said switching control signal for selectively applying to said check bit memory cell array a decode signal for reading out data from a corresponding column address of said memory cell array.
Claim 4
Dependent Claim
20 words
A semiconductor memory device in accordance with claim 2, wherein said switching control means comprises a column address strobe signal.
Claim 5
Dependent Claim
20 words
A semiconductor memory device in accordance with claim 2, further comprising internal shift register means for storing a column address.
Claim 6
Dependent Claim
31 words
A semiconductor memory device in accordance with claim 4, wherein said decode signal is a signal for reading out data from a column address stored by said internal shift register means.
Claim 7
Dependent Claim
30 words
A semiconductor memory device in accordance with claim 1, wherein said control signal comprises a signal which changes logical value at a timing responsive to a column address strobe signal.
Claim 8
Dependent Claim
233 words
A semiconductor memory evice having on-chip error checking and correcting functions, comprising: a plurality of memory cell arrays, said arrays including at least one data bit memory cell array for storing data bits and at least one check bit memory cell array for storing data including check bits; switching control means, said switching control means comprising a column address strobe signal; on-chip error checking and correcting means for generating said check bits in response to said data bits and for correcting said data bits in response to said check bits; means for disabling said on-chip error checking and correcting means in response to an external control signal; data input means for receiving data information; data writing means for writing said data information into said data bit memory cell array of said memory cell arrays and for writing said check bits generated by said on-chip checking and correcting means into said check bit memory cell array of said memory cell array; and data reading means for reading out data information and check bits from said memory cell arrays, said data reading means including a single data output terminal and switching means responsive to said switching control means for alternatingly accessing said check bit memory cell array and said data bit memory cell array so that check bits and data bits can be outputted from said single data output terminal successively in an interleaved manner.
Claim 9
Dependent Claim
233 words
A semiconductor memory evice having on-chip error checking and correcting functions, comprising: a plurality of memory cell arrays, said arrays including at least one data bit memory cell array for storing data bits and at least one check bit memory cell array for storing data including check bits; switching control means, said switching control means comprising a column address strobe signal; on-chip error checking and correcting means for generating said check bits in response to said data bits and for correcting said data bits in response to said check bits; means for disabling said on-chip error checking and correcting means in response to an external control signal; data input means for receiving data information; data writing means for writing said data information into said data bit memory cell array of said memory cell arrays and for writing said check bits generated by said on-chip checking and correcting means into said check bit memory cell array of said memory cell array; and data reading means for reading out data information and check bits from said memory cell arrays, said data reading means including a single data output terminal and switching means responsive to said switching control means for alternatingly accessing said check bit memory cell array and said data bit memory cell array so that check bits and data bits can be outputted from said single data output terminal successively in an interleaved manner.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-02-19 | 1993-08-21 | 1994-02-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-02-19 | 1997-08-21 | 1998-02-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-02-19 | 2001-08-21 | 2002-02-20 | $7700.00 | Window Closed / Lapsed |